參數(shù)資料
型號(hào): M38869FFAGP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù): 6/110頁(yè)
文件大小: 1601K
代理商: M38869FFAGP
6
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
P5
1
/INT
20
/S
0
P5
2
/INT
30
/R
P5
3
/INT
40
/W
P5
4
/CNTR
0
P5
5
/CNTR
1
Functions
Name
Pin
P4
0
/X
COUT
P4
1
/X
CIN
I/O port P4
8-bit I/O port with the same function as port P0.
<Input level>
P4
0
, P4
1
: CMOS input level
P4
2
–P4
6
: CMOS compatible input level or TTL in-
put level
P4
7
: CMOS compatible input level or TTL input
level in the bus interface function
<Output structure>
P4
0
, P4
1
, P4
7
: CMOS 3-state output structure
P4
2
–P4
6
: CMOS 3-state output structure or N-
channel open-drain output structure
Regardless of input or output port, P4
2
to P4
6
can
be input every pin level.
When P4
2
and P4
3
are used as output port, the
function which makes P4
2
and P4
3
clear to “0”
when the host CPU reads the output data bus
buffer 0 can be added.
8-bit I/O port with the same function as port P0.
CMOS compatible input level.
CMOS 3-state output structure.
P5
0
to P5
3
can be switched between CMOS com-
patible input level or TTL input level in the bus
interface function.
Function except a port function
Table 2 Pin description (2)
Sub-clock generating circuit I/O
pins
(Connect a resonator.)
P4
2
/INT
0
/OBF
00
P4
3
/INT
1
/OBF
01
P4
4
/RxD
P4
5
/TxD
P4
6
/S
CLK1
/OBF
10
P4
7
/S
RDY1
/S
1
P5
0
/A
0
P5
6
/DA
1
/PWM
01
P5
7
/DA
2
/PWM
11
P6
0
/AN
0
P6
7
/AN
7
P7
0
/S
IN2
P7
1
/S
OUT2
P7
2
/S
CLK2
P7
3
/S
RDY2
/INT
21
P7
4
/INT
31
P7
5
/INT
41
P7
6
/S
DA
P7
7
/S
CL
P8
0
/DQ
0
P8
7
/DQ
7
I/O port P5
I/O port P6
I/O port P7
I/O port P8
8-bit I/O port with the same function as port P0.
CMOS compatible input level.
CMOS 3-state output structure.
8-bit I/O port with the same function as port P0.
P7
0
–P7
5
: CMOS compatible input level or TTL in-
put level
P7
6
, P7
7
: CMOS compatible input level or
SMBUS input level in the I
2
C-BUS inter-
face function, N-channel open-drain
output structure
Regardless of input or output port, P7
0
to P7
5
can
be input every pin level.
8-bit I/O port with the same function as port P0.
CMOS compatible input level.
CMOS 3-state output structure.
CMOS compatible input level or TTL input level in
the bus interface function.
Interrupt input pins
Bus interface function pins
Serial I/O1 function pins
Serial I/O1 function pins
Bus interface function pins
Bus interface function pins
Interrupt input pins
Bus interface function pins
Timer X, timer Y function pins
D-A converter output pin
PWM output pin
A-D converter output pin
Serial I/O2 function pin
Serial I/O2 function pin
Interrupt input pin
Interrupt input pin
I
2
C-BUS interface function pin
Bus interface function pin
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