參數(shù)資料
型號(hào): M38867M8A-XXXHP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù): 30/113頁(yè)
文件大小: 1871K
代理商: M38867M8A-XXXHP
20
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Interrupt Request
Generating Conditions
Remarks
Interrupt Source
Low
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
High
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Table 6 Interrupt vector addresses and priority
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Vector Addresses (Note 1)
Reset (Note 2)
INT0
Input buffer full
(IBF)
INT1
Output buffer
empty (OBE)
Serial I/O1
reception
Serial I/O1
transmission
SCL, SDA
Timer X
Timer Y
Timer 1
Timer 2
CNTR0
SCL, SDA
CNTR1
Key-on wake-up
Serial I/O2
I2C
INT2
I2C
INT3
INT4
A-D converter
Key-on wake-up
BRK instruction
At reset
At detection of either rising or
falling edge of INT0 input
At input data bus buffer writing
At detection of either rising or
falling edge of INT1 input
At output data bus buffer read-
ing
At completion of serial I/O1 data
reception
At completion of serial I/O1
transfer shift or when transmis-
sion buffer is empty
At detection of either rising or
falling edge of SCL or SDA
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of SCL or SDA
At detection of either rising or
falling edge of CNTR1 input
At falling of port P3 (at input) in-
put logical level AND
At completion of serial I/O2 data
transfer
At completion of data transfer
At detection of either rising or
falling edge of INT2 input
At completion of data transfer
At detection of either rising or
falling edge of INT3 input
At detection of either rising or
falling edge of INT4 input
At completion of A-D conversion
At falling of port P3 (at input) in-
put logical level AND
At BRK instruction execution
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
External interrupt
(active edge selectable)
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (falling valid)
Valid when serial I/O2 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (falling valid)
Non-maskable software interrupt
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