參數(shù)資料
型號： M38867M8A-A07HP
廠商： Mitsubishi Electric Corporation
英文描述： connectors
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 46/110頁
文件大?。?/td> 1601K
代理商： M38867M8A-A07HP
46
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
+ 2 cycles (3.375
μ
s)
+ 1 cycle < 4.0
μ
s (3.25
μ
s)
Fig. 43 START condition detecting timing diagram
START/STOP Condition Detecting Operation
The START/STOP condition detection operations are shown in
Figures 43, 44, and Table 13. The START/STOP condition is set
by the START/STOP condition set bit.
The START/STOP condition can be detected only when the input
signal of the S
CL
and S
DA
pins satisfy three conditions: S
CL
re-
lease time, setup time, and hold time (see Table 13).
The BB flag is set to “1” by detecting the START condition and is
reset to “0” by detecting the STOP condition.
The BB flag set/reset timing is different in the standard clock mode
and the high-speed clock mode. Refer to Table 13, the BB flag set/
reset time.
Note:
When a STOP condition is detected in the slave mode (MST = 0), an
interrupt request signal “I
2
CIRQ” occurs to the CPU.
Table 13 START condition/STOP condition detecting conditions
Note:
Unit : Cycle number of system clock
φ
SSC value is the decimal notation value of the START/STOP condi-
tion set bits SSC4 to SSC0. Do not set “0” or an odd number to SSC
value. The value in parentheses is an example when the I
2
C START/
STOP condition control register is set to “18
16
” at
φ
= 4 MHz.
Fig. 44 STOP condition detecting timing diagram
S
CL
release time
Standard clock mode
SSC value + 1 cycle (6.25
μ
s)
High-speed clock mode
4 cycles (1.0
μ
s)
2 cycles (1.0
μ
s)
2 cycles (0.5
μ
s)
3.5 cycles (0.875
μ
s)
SSC value
2
SSC value
2
SSC value –1
2
Setup time
Hold time
BB flag set/
reset time
cycle < 4.0
μ
s (3.0
μ
s)
START Condition Generating Method
When writing “1” to the MST, TRX, and BB bits of the I
2
C status
register (address 0014
16
) at the same time after writing the slave
address to the I
2
C data shift register (address 0012
16
) with the
condition in which the ES0 bit of the I
2
C control register (address
0015
16
) and the BB flag are “0”, a START condition occurs. After
that, the bit counter becomes “000
2
” and an S
CL
for 1 byte is out-
put. The START condition generating timing is different in the
standard clock mode and the high-speed clock mode. Refer to
Figure 41, the START condition generating timing diagram, and
Table 11, the START condition generating timing table.
STOP Condition Generating Method
When the ES0 bit of the I
2
C control register (address 0015
16
) is
“1,” write “1” to the MST and TRX bits, and write “0” to the BB bit
of the I
2
C status register (address 0014
16
) simultaneously. Then a
STOP condition occurs. The STOP condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 42, the STOP condition generating timing
diagram, and Table 12, the STOP condition generating timing
table.
Fig. 41 START condition generating timing diagram
Fig. 42 STOP condition generating timing diagram
Table 12 STOP condition generating timing table
Item
Setup
time
START/STOP condition
generating selection bit
“0”
“1”
“0”
“1”
Standard
clock mode
5.5
μ
s (22 cycles)
13.5
μ
s (54 cycles)
5.5
μ
s (22 cycles)
13.5
μ
s (54 cycles)
Note:
Absolute time at
φ
= 4 MHz. The value in parentheses denotes the
number of
φ
cycles.
High-speed
clock mode
3.0
μ
s (12 cycles)
7.0
μ
s (28 cycles)
3.0
μ
s (12 cycles)
7.0
μ
s (28 cycles)
Table 11 START condition generating timing table
Item
Setup
time
START/STOP condition
generating selection bit
“0”
“1”
“0”
“1”
Standard
clock mode
5.0
μ
s (20 cycles)
13.0
μ
s (52 cycles)
5.0
μ
s (20 cycles)
13.0
μ
s (52 cycles)
Note:
Absolute time at
φ
= 4 MHz. The value in parentheses denotes the
number of
φ
cycles.
High-speed
clock mode
2.5
μ
s (10 cycles)
6.5
μ
s (26 cycles)
2.5
μ
s (10 cycles)
6.5
μ
s (26 cycles)
Hold
time
Hold
time
I
2
C
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