參數(shù)資料
型號: M38867E8AHP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 5 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù): 92/113頁
文件大?。?/td> 1871K
代理商: M38867E8AHP
5
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
VCC, VSS
PIN DESCRIPTION
Functions
Name
Pin
Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss.
In the flash memory version, apply voltage of 4.0 V – 5.5 V to Vcc, and 0 V to Vss
This pin controls the operation mode of the chip.
Normally connected to VSS.
If this pin is connected to Vcc, the internal ROM is inhibited and an external memory is accessed.
In the flash memory version, connected to VSS.
In the EPROM version or the flash memory version, this pin functions as the VPP power source input pin.
Reference voltage input pin for A-D and D-A converters.
Analog power source input pin for A-D and D-A converters.
Connect to VSS.
Reset input pin for active “L”.
Input and output pins for the clock generating circuit.
Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
When an external clock is used, connect the clock source to the XIN pin and leave the XOUT
pin open.
8-bit CMOS I/O port.
I/O direction register allows each pin to be individually
programmed as either input or output.
When the external memory is used, these pins are used as the address bus.
CMOS compatible input level.
CMOS 3-state output structure or N-channel open-drain output structure.
8-bit CMOS I/O port.
I/O direction register allows each pin to be individually programmed as either input or output.
When the external memory is used, these pins are used as the address bus.
CMOS compatible input level.
CMOS 3-state output structure or N-channel open-drain output structure.
8-bit CMOS I/O port.
I/O direction register allows each pin to be individually programmed as either input or output.
When the external memory is used, these pins are used as the data bus.
CMOS compatible input level.
CMOS 3-state output structure.
P24 to P27 (4 bits) are enabled to output large current for LED drive (only in single-chip mode).
8-bit CMOS I/O port.
I/O direction register allows each pin to be individually
programmed as either input or output.
When the external memory is used, these pins are
used as the control bus.
CMOS compatible input level.
CMOS 3-state output structure.
These pins function as key-on wake-up and compara-
tor input.
These pins are enabled to control pull-up.
Power source
Table 1 Pin description (1)
Function except a port function
Comparator reference power source
input pin
Key-on wake-up input pin
Comparator input pin
PWM output pin
Key-on wake-up input pin
Comparator input pin
Reference voltage
Analog power source
Clock input
Clock output
I/O port P0
I/O port P1
I/O port P2
VREF
AVSS
P30/PWM00
P31/PWM10
CNVSS input
CNVSS
RESET
Reset input
XIN
XOUT
P00/P3REF
P01–P07
P10–P17
P20–P27
I/O port P3
P32–P37
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