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參數(shù)資料
| 型號： | M38749EFT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 6.4 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 14 MM, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 318/358頁 |
| 文件大?。?/td> | 4216K |
| 代理商： | M38749EFT |
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1-47
HARDWARE
FUNCTIONAL DESCRIPTION
3874 Group User’s Manual
Fig. 39 Structure of serial I/O3 automatic transfer data pointer
(1) 8-bit serial I/O mode
Address 001316 is the serial I/O3 register. When selecting an inter-
nal synchronous clock, serial transfer of the 8-bit serial I/O starts
by the write signal to the serial I/O3 register (address 001316).
The serial transfer status flag of the serial I/O3 control register 2
indicates the serial I/O3 register status. The flag is set to “1” by a
serial I/O3 register write, which triggers a transfer start. After the
8-bit transfer is completed, the flag is reset to “0” and a serial I/O3
interrupt request occurs simultaneously.
When an external synchronous clock is selected, the contents of
the serial I/O3 register are continually shifted while the transfer
clock inputs to SCLK3. In this case, control the clock externally.
(2) Automatic transfer serial I/O mode
Since read and write to the serial I/O3 register are controlled by
the serial I/O3 automatic transfer controller, address 001316 func-
tions as the transfer counter (in byte units).
In order to make a serial transfer through the serial I/O3 automatic
transfer RAM (addresses 020016 to 02FF16), it is necessary to set
the serial I/O3 automatic transfer data pointer before transferring
data. The automatic transfer data pointer set bits indicate the low-
order 8 bits of the start data stored address. The automatic
transfer RAM transmit/receive address select bit can divide the
256-byte serial I/O3 automatic transfer RAM into two areas: 128-
byte transmit data area and 128-byte receive data area.
When an internal synchronous clock is selected and any of the fol-
lowing conditions apply, the transfer interval between each 1-byte
data can be set by the automatic transfer interval set bits of the
serial I/O3 control register 3:
1. The handshake signal is not used.
2. The handshake signal’s SRDY3 output, SBUSY3 output, and
SSTB3 output are used independently.
3. The handshake signal’s output is used in groups: SRDY3/SSTB3
output or SBUSY3/SSTB3.
There are 32 values among 2 and 33 cycles of the transfer clock.
When the automatic transfer interval setting is valid and SBUSY3
output is used, and the SBUSY3 and SSTB3 output function as sig-
nal for each transfer data set by the SBUSY3 outputSSTB3 output
function selection bit, there is the transfer interval before the first
data is transmitted/received, as well as after the last data is trans-
mitted/received. When using SSTB3 output, regardless of the
contents of the SBUSY3 output SSTB3 output function selection
bit, this transfer interval become 2 cycles longer than the value set
for each 1-byte data. In addition, when using the combined output
of SBUSY3 and SSTB3 as the signal for each transfer data set, the
transfer interval after completion of transmission/receipt of the last
data become 2 cycles longer than the set value.
When selecting an external synchronous clock, the automatic
transfer interval cannot be set.
After all of the above bit settings have been completed, and an in-
ternal synchronous clock has been selected, serial automatic
transfer starts when the value of the number of transfer bytes,
decremented by 1, is written to the transfer counter (address
001316). When an external synchronous clock is selected, write
the value of the transfer bytes, decremented by 1, to the transfer
counter, and input the transfer clock to SCLK3 after 5 or more
cycles of internal clock
φ.
Set the transfer interval of each 1-byte data transmission to 5 or
more cycles of the internal clock
φ after the rising edge of the last
bit of a 1-byte data.
Regardless of internal or external synchronous clock, the auto-
matic transfer data pointer and transfer counter are both
decremented after receipt of each 1-byte data is completed and it
is written to the automatic transfer RAM. The serial transfer status
flag is set to “1” by writing to the transfer counter which triggers
the start of transmission. After the last data is written to the auto-
matic transfer RAM, the serial transfer status flag is set to “0” and
a serial I/O3 interrupt request occurs simultaneously.
The write values of the automatic transfer data pointer set bits and
the automatic transfer interval set bits are kept in the latch. As a
transfer counter write occurs, each value is transferred to its corre-
sponding decrement counter.
b7
b0
Serial I/O3 automatic transfer data pointer
(SIO3DP : address 001716)
Automatic transfer data pointer set bits
Indicates the low-order 8 bits of the address stored the start data on the
serial I/O3 automatic transfer RAM.
Write: kept in latch
Read: from decrement counter
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M38749EFT-XXXFS | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38749EFT-XXXGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38749M4D-XXXFS | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38749M4D-XXXGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38749M4F-XXXFS | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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