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| 型號： | M38749EFT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 6.4 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 14 MM, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 233/358頁 |
| 文件大?。?/td> | 4216K |
| 代理商： | M38749EFT |
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3874 Group User's Manual
APPENDIX
3-49
3.5 Control Registers
Fig. 3.5.10 Structure of serial I/O1 control register
Notes 1: When selecting clock synchronous serial I/O
Stop of transmission operation
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the serial I/O1 enable bit and the transmit enable bit to “0” (serial I/O and transmit
disabled).
Stop of receive operation
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled), or clear the serial I/O1 enable bit to
“0” (serial I/O disabled).
Stop of transmit/receive operation
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear both the transmit enable bit and receive enable bit to “0” (transmit and receive
disabled).
(when data is transmitted and received in the clock synchronous serial I/O mode, any one of data
transmission and reception cannot be stopped.)
2: When selecting clock asynchronous serial I/O
Stop of transmission operation
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
Stop of receive operation
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled).
Stop of transmit/receive operation
Only transmission operation is stopped
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the transmit enable bit to “0” (transmit disabled).
Only receive operation is stopped
As for the serial I/O1 that can be used as either a clock synchronous or an asynchronous (UART)
serial I/O, clear the receive enable bit to “0” (receive disabled).
3: When an external clock is used as the synchronous clock for data transmission, set the transmit
enable bit to “1” at “H” of the SCLK1 input level. Also, write data to the transmit buffer register at “H” of
the SCLK1 input level.
4: When an external clock input is selected as the synchronous clock and the receiver perform the
SRDY1 output, set “1” to the transmit enable bit in addition to the receive enable bit and the SRDY1
output enable bit.
5: When an external clock input is selected as the synchronous clock, set “1” to the transmit enable bit
while the synchronous clock is “H” state.
6: Transmit interrupt request when transmit enable bit is set
The transmiit interrupt request bit is set and the interrupt request occurs even when selecting timing
that either of the following flags is set to “1” as timing where the transmit interrupt occurs.
Transmit buffer empty flag is set to “1”
Transmit shift register completion flag is set to “1”
Accordingly, when the transmit interrupt is used, set the transmit interrupt enable bit to transmit
enabled as the following sequence.
Transmit enable bit is set to “1”
Transmit interrupt request bit is set to “0”
7: In order to stop a transmit, set the transmit enable bit to “0” (transmit disable).
Do not set only the serial I/O1 enable bit to “0”.
8: A receive operation can be stopped by either setting the receive enable bit to “0” or the serial I/O1
enable bit to “0”.
9: To stop a transmit when transferring in clock synchronous serial I/O mode, set both the transmit
enable bit and the receive enable bit to “0” at the same time.
10: To set the serial I/O1 control register again, first set the transmit enable/receive enable bits to “0”.
Next, reset the transmit/receive circuits, and, finally, reset the serial I/O1 control register.
11: Note when confirming the transmit shift register completion flag and controlling the data transmit after
writing a transmit data to the transmit buffer. There is a delay of 0.5 to 1.5 shift clock cycles while the
transmit shift register completion flag goes from “1” to “0”.
Serial I/O1 control register
b7 b6 b5 b4 b3 b2 b1 b0
Serial I/O1 control register
(SIO1CON: address 1A16)
b
0
Name
0
Functions
At reset R W
1
0
2
0
3
0
4
0
0: Transmit disabled
1: Transmit enabled
5
0
Receive enable bit
(RE)
7
0
6
0
0: Clock asynchronous
serial I/O (UART) mode
1: Clock synchronous
serial I/O mode
0: Serial I/O1 disabled
(pins P44–P47 operate
as normal I/O pins)
1: Serial I/O1 enabled
(pins P44–P47 operate
as serial I/O pins)
0: When transmit buffer
has emptied
1: When transmit shift
operation is completed
BRG count source
selection bit (CSS)
Serial I/O1
synchronous clock
selection bit
(SCS)
Serial I/O1 mode
selection bit (SIOM)
Serial I/O1 enable
bit (SIOE)
Transmit interrupt
source selection bit
(TIC)
0: f(XIN)
1: f(XIN)/4
In clock synchronous
mode
0: BRG output/4
1: External clock input
In UART mode
0: BRG output/16
1: External clock input/16
Transmit enable bit
(TE)
0: Receive disabled
1: Receive enabled
SRDY1 output
enable bit (SRDY)
0: P47/SRDY1 pin operates
as normal I/O port P47
1: P47/SRDY1 pin operates
as signal output pin
SRDY1
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