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參數(shù)資料
| 型號(hào)： | M38504E6-XXXSP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 30/99頁 |
| 文件大?。?/td> | 1384K |
| 代理商： | M38504E6-XXXSP |
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30
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3850 Group (Spec. H/A)
TIMERS
The 3850 group (spec. H/A) has four timers: timer X, timer Y, timer
1, and timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches
“
00
16
”
, an un-
derflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to
“
1
”
.
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating
modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts the count source selected by Timer count source
selection bit.
(2) Pulse Output Mode
The timer counts the count source selected by Timer count source
selection bit. Whenever the contents of the timer reach
“
00
16
”
, the
signal output from the CNTR
0
(or CNTR
1
) pin is inverted. If the
CNTR
0
(or CNTR
1
) active edge selection bit is
“
0
”
, output begins
at
“
H
”
.
If it is
“
1
”
, output starts at
“
L
”
. When using a timer in this mode, set
the corresponding port P2
7
( or port P4
0
) direction register to out-
put mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR
0
or
CNTR
1
pin.
When the CNTR
0
(or CNTR
1
) active edge selection bit is
“
0
”
, the
rising edge of the CNTR
0
(or CNTR
1
) pin is counted.
When the CNTR
0
(or CNTR
1
) active edge selection bit is
“
1
”
, the
falling edge of the CNTR
0
(or CNTR
1
) pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR
0
(or CNTR
1
) active edge selection bit is
“
0
”
, the timer
counts the selected signals by the count source selection bit while
the CNTR
0
(or CNTR
1
) pin is at
“
H
”
. If the CNTR
0
(or CNTR
1
) ac-
tive edge selection bit is
“
1
”
, the timer counts it while the CNTR
0
(or CNTR
1
) pin is at
“
L
”
.
The count can be stopped by setting
“
1
”
to the timer X (or timer Y)
count stop bit in any mode. The corresponding interrupt request
bit is set each time a timer underflows.
Fig. 23 Structure of timer XY mode register
I
Note
When switching the count source by the timer 12, X and Y count
source bits, the value of timer count is altered in unconsiderable
amount owing to generating of a thin pulses in the count input
signals.
Therefore, select the timer count source before set the value to
the prescaler and the timer.
When timer X/timer Y underflow while executing the instruction
which sets
“
1
”
to the timer X/timer Y count stop bits, the timer X/
timer Y interrupt request bits are set to
“
1
”
. Timer X/Timer Y in-
terrupts are received if these interrupts are enabled at this time.
The timing which interrupt is accepted has a case after the in-
struction which sets
“
1
”
to the count stop bit, and a case after
the next instruction according to the timing of the timer under-
flow. When this interrupt is unnecessary, set
“
0
”
(disabled) to the
interrupt enable bit and then set
“
1
”
to the count stop bit.
Fig. 24 Structure of timer count source selection register
Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency
which is selected by timer 12 count source selection bit. The out-
put of prescaler 12 is counted by timer 1 and timer 2, and a timer
underflow sets the interrupt request bit.
T
i
m
0
1
e
C
:
C
r
o
o
X
u
u
c
n
n
o
t
t
u
s
s
n
t
a
t
o
t
r
p
s
t
t
o
p
b
i
t
:
Timer XY mode register
(TM : address 0023
16
)
i
m
e
r
X
o
p
e
b1b0
Timer Y operating mode bits
0 0: Timer mode
0 1: Pulse output mode
1 1: Pulse width measurement mode
N
T
R
1
a
c
t
i
v
e
e
d
g
e
0
:
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Timer Y count stop bit
0: Count start
1: Count stop
C
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e
s
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t
b
7
CNTR
0
active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
b
0
T
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a
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i
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)
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)
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)
(
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CIN
)/16 at low-speed mode)
Timer 1)/16 (f(X
CIN
)
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d
(
r
e
t
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r
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s
“
0
”
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)
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