參數(shù)資料
型號(hào): M38503G4AFP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDSO42
封裝: 8.40 X 17.5 MM, 0.80 MM PITCH, PLASTIC, SSOP-42
文件頁(yè)數(shù): 26/59頁(yè)
文件大?。?/td> 885K
代理商: M38503G4AFP
Rev.2.13
Apr 17, 2009
Page 32 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 31. Structure of PWM control register
Fig 32. PWM output timing when PWM register or PWM prescaler is changed
<Notes>
The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin.
The length of this “L” level output is as follows:
(Count source selection bit = 0, where n is the value set in the prescaler)
(Count source selection bit = 1, where n is the value set in the prescaler)
b0
PWM control register
(PWMCON : address 001D16)
PWM function enable bit
0: PWM disabled
1: PWM enabled
Count source selection bit
0: f(XIN) (f(XCIN) at low-speed mode)
1: f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Not used (return “0” when read)
b7
PWM output
T
T2
B
C
PWM register
write signal
PWM prescaler
write signal
(Changes “H” term from “A” to “ B”.)
(Changes PWM period from “T” to “T2”.)
B
T
C
T2
=
When the contents of the PWM register or PWM prescaler have changed,
the PWM output will change from the next period after the change.
A
n1
+
2
×fXIN
()
----------------------- sec
n1
+
fXIN
()
---------------- sec
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