參數(shù)資料
型號： M38503G4AFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDSO42
封裝： 8.40 X 17.5 MM, 0.80 MM PITCH, PLASTIC, SSOP-42
文件頁數(shù)： 11/59頁
文件大?。?/td> 885K
代理商： M38503G4AFP
Rev.2.13
Apr 17, 2009
Page 19 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
INTERRUPTS
Interrupts occur by 15 sources among 15 sources: six external,
eight internal, and one software.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an
interrupt enable bit, and the interrupt disable flag except for the
software interrupt set by the BRK instruction. An interrupt
occurs if the corresponding interrupt request and enable bits are
“1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The
I (interrupt disable) flag disables all interrupts except the BRK
instruction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt Operation
By acceptance of an interrupt, the following operations are
automatically performed:
1. The contents of the program counter and the processor sta-
tus register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding inter-
rupt request bit is cleared.
3. The interrupt jump destination address is read from the vec-
tor table into the program counter.
<Notes>
When setting the followings, the interrupt request bit may be set
to “1”.
When setting external interrupt active edge
Related register: Interrupt edge selection register
(address 003A16)
Timer XY mode register (address 002316)
When switching interrupt sources of an interrupt vector
address where two or more interrupt sources are allocated
Related register: Interrupt edge selection register (address
003A16)
When not requiring for the interrupt occurrence synchronized
with these setting, take the following sequence.
(1) Set the corresponding interrupt enable bit to “0” (disabled).
(2) Set the interrupt edge select bit (the active edge selection
bit) or the interrupt source select.
(3) Set the corresponding interrupt request bit to “0” after 1 or
more instructions have been executed.
(4) Set the corresponding interrupt enable bit to “1” (enabled).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M38503G4AFP#U1 功能描述:IC 740/3850 MCU QZ-ROM 42SSOP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 標準包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI，I²C，UART/USART 外圍設(shè)備:POR，PWM，WDT 輸入/輸出數(shù):40 程序存儲器容量:- 程序存儲器類型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC（J 形引線） 包裝:帶卷 (TR)
M38503G4ASP#U1 功能描述:IC 740/3850 MCU QZ-ROM 42DIP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/38000 標準包裝:250 系列:80C 核心處理器:8051 芯體尺寸:8-位 速度:16MHz 連通性:EBI/EMI，I²C，UART/USART 外圍設(shè)備:POR，PWM，WDT 輸入/輸出數(shù):40 程序存儲器容量:- 程序存儲器類型:ROMless EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-LCC（J 形引線） 包裝:帶卷 (TR)
M38503M2404F 制造商:Panasonic Industrial Company 功能描述:IC
M38503M4A-210SP 制造商:Renesas Electronics Corporation 功能描述:
M38504E6FP 制造商:Renesas Electronics Corporation 功能描述:MCU 3/5V 24K 42-SSOP - Trays
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