參數(shù)資料
型號(hào): M38275EAMXXXFS
廠商: Mitsubishi Electric Corporation
英文描述: Dual Low-Power Rail-to-Rail Input/Output Op Amp w/Shutdown 10-MSOP-PowerPAD 0 to 70
中文描述: 單芯片8位CMOS微機(jī)
文件頁數(shù): 8/70頁
文件大?。?/td> 1112K
代理商: M38275EAMXXXFS
8
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
3827 Group
MITSUBISHI MICROCOMPUTERS
Not available
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
Stack page selection bit
0 : 0 page
1 : 1 page
Not used (returns “1” when read)
(Do not write “0” to this bit.)
Port X
C
switch bit
0 : Stop oscillating
1 : X
CIN
, X
COUT
Main clock ( X
IN
-X
OUT
) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bit
0 : X
IN
/2 (high-speed mode)
1 : X
IN
/8 (middle-speed mode)
Internal system clock selection bit
0 : X
IN
-X
OUT
selected (middle-/high-speed mode)
1 : X
CIN
-X
COUT
selected (low-speed mode)
CPU mode register
(CPUM (CM) : address 003B
16
)
b7
b0
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 3827 group uses the standard 740 family instruction set. Re-
fer to the table of 740 family addressing modes and machine
instructions or the 740 Family Software Manual for details on the
instruction set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
[CPU Mode Register (CPUM)] 003B
16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit.
The CPU mode register is allocated at address 003B
16
.
Fig. 6 Structure of CPU mode register
相關(guān)PDF資料
PDF描述
M38275EAMXXXGP Dual Low-Power Rail-to-Rail Input/Output Op Amp w/Shutdown 14-SOIC 0 to 70
M38275EAMXXXHP Dual Low-Power Rail-to-Rail Input/Output Op Amp w/Shutdown 14-SOIC 0 to 70
M38275EBMXXXFS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38275EBMXXXGP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38275EBMXXXHP Dual Low-Power Rail-to-Rail Input/Output Op Amp w/Shutdown 10-MSOP-PowerPAD -40 to 125
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