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2. APPLICAT ION
3819 Group USER’S MANUAL
MITSUBISHI MICROCOMPUTER
3819 Group
2.7 Zero cross detection circuit
Control procedure :
Set the related registers according to Figure 2.7.8.
At the falling edge of the commercial frequency (50 Hz or 60 Hz), the ZCR interrupt occurs.
The clock is counted up every second in the ZCR interrupt processing routine.
Figure 2.7.9 shows a control procedure.
Fig. 2.7.9 Control procedure [Clock count using ZCR interrupt (using a noise filter)]
ZCR interrupt processing routine
(
Note 1
)
CLT (
Note 2
)
CLD (
Note 3
)
Push register to stack
RTI
~
RESET
Initialization
SEI
CLT
CLD
.
ZCRCON
Wait of 2 sampling clocks
IREQ1
NOP
ICON1
1 second counter
(.
CLI
(Address:3B
16
), bit6
(Address:39
16
)
(Address:3C
16
), bit1
(Address:3E
16
), bit1
0
00000001
2
0
1
50(60)
= 0
1 second counter = 0
1 second counter – 1
1 second counter 50(60)
Clock count up (second–year)
Pop registers
All interrupts : Disabled
Main clock division ratio : select the high-speed
mode
Setting of the Zero cross detection control register
Set the INT
1
/ZCR interrupt request bit to “0”
ZCR interrupt : Enabled
Input 50 Hz (60 Hz)
Interrupts : Enabled
Note 2 :
When using the index X mode flag (T).
Note 3 :
When using the decimal mode flag (D).
Push into the register used in the interrupt
processing routine.
Input 50 Hz (60 Hz)
Pop registers which is pushed to stack
Note 1 :
The ZCR interrupt occurs with delay of the
Zero cross by a minimum of 1 sampling
clock or a maximum of 2 sampling clocks
because a noise filter is used.
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