![](http://datasheet.mmic.net.cn/30000/M38197MA-XXXKP_datasheet_2360287/M38197MA-XXXKP_47.png)
33
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
G1 (SEG PA)
0F8016
FLD automatic
display RAM
G2 (SEG PA)
G15 (SEG PA)
G16 (SEG PA)
G1 (SEG P8)
G2 (SEG P8)
0F8F16
0F9016
G15 (SEG P8)
G16 (SEG P8)
G1 (SEG P9)
G2 (SEG P9)
0F9F16
0FA016
G15 (SEG P9)
G16 (SEG P9)
G1 (SEG P3)
G2 (SEG P3)
0FAF16
0FB016
G15 (SEG P3)
G16 (SEG P3)
G1 (SEG P0)
G2 (SEG P0)
0FBF16
0FC016
G15 (SEG P0)
G16 (SEG P0)
G1 (SEG P1)
G2 (SEG P1)
0FCF16
0FD016
G15 (SEG P1)
G16 (SEG P1)
0FDF16
Local
address bus
Main
address bus
Address
decoder
FLD data pointer
(address 003816)
FLD data pointer
reload register
(address 003816)
Timing
generator
FLD blanking interrupt
FLD digit interrupt
PA1/SEG1
S/P
PA0/SEG0
S/P
PA2/SEG2
S/P
PA3/SEG3
S/P
PA4/SEG4
S/P
PA5/SEG5
S/P
PA6/SEG6
S/P
PA7/SEG7
S/P
001416
003516
8
P81/SEG9
S/P
P80/SEG8
S/P
P82/SEG10
S/P
P83/SEG11
S/P
P84/SEG12
S/P
P85/SEG13
S/P
P86/SEG14
S/P
P87/SEG15
S/P
001016
003416
8
P91/SEG17
P90/SEG16
P92/SEG18
P93/SEG19
P94/SEG20
P95/SEG21
P96/SEG22
P97/SEG23
001216
8
P01/SEG33/DIG1
S/D
P00/SEG32/DIG0
S/D
P02/SEG34/DIG2
S/D
P03/SEG35/DIG3
S/D
P04/SEG36/DIG4
S/D
P05/SEG37/DIG5
S/D
P06/SEG38/DIG6
S/D
P07/SEG39/DIG7
S/D
000016
003216
8
P21/DIG17
D/P
P20/DIG16
D/P
P22/DIG18
D/P
P23/DIG19
D/P
4
FLDC mode
register 1
(address 003616)
P11/SEG41/DIG9
S/D
P10/SEG40/DIG8
S/D
P12/DIG10
P13/DIG11
P14/DIG12
P15/DIG13
P16/DIG14
P17/DIG15
000216
003716
8
P31/SEG25
P30/SEG24
P32/SEG26
P33/SEG27
P34/SEG28
P35/SEG29
P36/SEG30
P37/SEG31
000616
8
Main
data bus
Local
data bus
000416
003316
FLD CONTROLLER
The 3819 group has fluorescent display (FLD) drive and control
circuits.
The FLD controller consists of the following components:
42 pins for segments
20 pins for digits
FLDC mode register 1
FLDC mode register 2
FLD data pointer
FLD data pointer reload register
Port P0 segment/digit switch register
Port P2 digit/port switch register
Port PA segment/port switch register
Port P8 segment/port switch register
96-byte FLD automatic display RAM
The segment pins can be used from 16 up to 42 pins (maximum)
and the digit pins can be used from 6 up to 16 pins (maximum).
The segment and the digit pins can be used up to 52 pins (maxi-
mum) in total.
In the FLD automatic display mode ports P12 to P17 become digit
pins DIG10 to DIG15 automatically.
Fig. 27 FLD control circuit block diagram