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34
3819 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
FLDC Mode Registers (FLDM 1, FLDM 2)
003616, 003716
The FLDC mode register 1 (address 003616) and FLDC mode reg-
ister 2 (address 003716) are a seven bit register and an eight bit
register respectively which are used to control the FLD automatic
display and set the blanking time Tscan for key-scan.
Fig. 28 Structure of FLDC mode register 1
Fig. 29 Structure of FLDC mode register 2
Tscan control bits
b1 b0
0 0 : 0
FLD digit interrupt (at rising edge of each digit)
0 1 : 1 ! Tdisp
1 0 : 2 ! Tdisp
1 1 : 3 ! Tdisp
Toff control bits
(Setting of digit/segment OFF time)
b5 b4 b3 b2
0 0 0 0 : 1/16 ! Tdisp
0 0 0 1 : 2/16 ! Tdisp
0 0 1 0 : 3/16 ! Tdisp
0 0 1 1 : 4/16 ! Tdisp
0 1 0 0 : 5/16 ! Tdisp
0 1 0 1 : 6/16 ! Tdisp
0 1 1 0 : 7/16 ! Tdisp
0 1 1 1 : 8/16 ! Tdisp
1 0 0 0 : 9/16 ! Tdisp
1 0 0 1 : 10/16 ! Tdisp
1 0 1 0 : 11/16 ! Tdisp
1 0 1 1 : 12/16 ! Tdisp
1 1 0 0 : 13/16 ! Tdisp
1 1 0 1 : 14/16 ! Tdisp
1 1 1 0 : 15/16 ! Tdisp
1 1 1 1 : 16/16 ! Tdisp
Not used (returns “0” when read)
High-breakdown-voltage drivability selection bit
0 : Strong drivability
1 : Weak drivability
b7
FLDC mode register 1
(FLDM 1 : address 003616)
b0
FLD blanking interrupt
(at falling edge of the last digit)
Automatic display control bit(P0, P1, P2 0–P23, P3, P8, P9, PA)
0 : Ordinary mode
1 : Automatic display mode
Display start bit
0 : Display stopped
1 : Display in progress
(display starts by writing “1” to this bit which is set to “0”)
Tdisp control bits
(digit time setting, at 8 MHz oscillation frequency)
b5 b4 b3 b2
0 0 0 0 : 128
s
0 0 0 1 : 256
s
0 0 1 0 : 384
s
0 0 1 1 : 512
s
0 1 0 0 : 640
s
0 1 0 1 : 768
s
0 1 1 0 : 896
s
0 1 1 1 : 1024
s
1 0 0 0 : 1152
s
1 0 0 1 : 1280
s
1 0 1 0
1 1 1 1
Pl0 segment/digit switch bit
0 : Digit
1 : Segment
Pl1 segment/digit switch bit
0 : Digit
1 : Segment
b7
FLDC mode register 2
(FLDM 2 : address 003716)
b0
Not available