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3. APPENDIX
MITSUBISHI MICROCOMPUTER
3819 Group
3.3 Control registers
3819 Group USER’S MANUAL
Fig. 3.3.8 Structure of Serial I/O 3 control register
Fig. 3.3.7 Structure of Serial I/O 2 control register
Serial I/O 2 control register
b7 b6 b5 b4 b3 b2 b1 b0
B
Function
At reset
RW
0
1
2
3
4
5
6
0
Serial I/O 2 control register (SIO2CON) [Address:1D16]
Name
Internal synchronous clock
selection bits
Synchronous clock selection
bit
000 : f(XIN)/8 or f(XCIN)/8
001 : f(XIN)/16 or f(XCIN)/16
010 : f(XIN)/32 or f(XCIN)/32
011 : f(XIN)/64 or f(XCIN)/64
110 : f(XIN)/128 or f(XCIN)/128
111 : f(XIN)/256 or f(XCIN)/256
0 : External clock
1 : Internal clock
b2 b1b0
Serial I/O 2 port selection bit
(P51,P52 )
Transfer direction selection bit
0 : LSB first
1 : MSB first
SRDY2 output selection bit
(P53)
0 : I/O port
1 : SRDY2 signal pin
0 : I/O port
1 : SOUT2, SCLK2 signal pins
7 P51/SOUT2 P-channel output
disable bit
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
Serial I/O 3 control register
b7 b6 b5 b4 b3 b2 b1 b0
B
Function
R W
0
1
2
3
4
5
6
0
Serial I/O 3 control register (SIO3CON) [Address:1E16]
Name
Internal synchronous clock
selection bits
Synchronous clock selection
bit
000 : f(XIN)/8 or f(XCIN)/8
001 : f(XIN)/16 or f(XCIN)/16
010 : f(XIN)/32 or f(XCIN)/32
011 : f(XIN)/64 or f(XCIN)/64
110 : f(XIN)/128 or f(XCIN)/128
111 : f(XIN)/256 or f(XCIN)/256
0 : External clock
1 : Internal clock
b2 b1b0
Serial I/O 3 port selection bit
(P55,P56 )
Transfer direction selection
bit
0 : LSB first
1 : MSB first
SRDY3 output selection bit
(P57)
0 : I/O port
1 : SRDY3 signal pin
0 : I/O port
1 : SOUT3, SCLK3 signal pins
7
0
P55/SOUT3 P-channel output
disable bit
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
At reset
0