參數(shù)資料
型號(hào)： M38073E4FP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP80
封裝： 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù)： 61/74頁
文件大小： 1182K
代理商： M38073E4FP
64
MITSUBISHI MICROCOMPUTERS
3807 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
TIMING REQUIREMENTS
Table 18 Timing requirements (1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = – 20 to 85
°C, unless otherwise noted)
Min.
Typ.
Max.
Symbol
Parameter
Limits
Unit
____________
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RXD–SCLK1)
th(SCLK1–RXD)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2–SCLK2)
th(SCLK2–SIN2)
2
125
50
200
80
800
370
220
100
1000
400
200
s
ns
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “H” pulse width
INT0 to INT4 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 clock input set up time
Serial I/O1 clock input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input set up time
Serial I/O2 clock input hold time
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
Max.
Symbol
Parameter
Unit
Min.
Typ.
____________
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RXD–SCLK1)
th(SCLK1–RXD)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SIN2–SCLK2)
th(SCLK2–SIN2)
2
243
100
500
230
2000
950
400
200
2000
950
400
300
s
ns
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0 to INT4 input “H” pulse width
INT0 to INT4 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 clock input set up time
Serial I/O1 clock input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 clock input set up time
Serial I/O2 clock input hold time
Note: When bit 6 of address 001A16 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 001A16 is “0” (UART).
Table 19 Timing requirements (2) (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = – 20 to 85
°C, unless otherwise noted)
Limits
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