參數(shù)資料
型號(hào)： M38073E4FP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP80
封裝： 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù)： 10/74頁(yè)
文件大小： 1182K
代理商： M38073E4FP
18
MITSUBISHI MICROCOMPUTERS
3807 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Fig. 14. Structure of Interrupt-related registers
b7
b0
b7
b0
b7
b0
b7
b0
b7
b0
Interrupt edge selection register
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
INT2 interrupt edge selection bit
INT3 interrupt edge selection bit
INT4 interrupt edge selection bit
Timer 1/INT2 interrupt source bit
Timer 2/INT3 interrupt source bit
Timer 3/INT4 interrupt source bit
(INTEDGE : address 003A16)
0 : Falling edge active
1 : Rising edge active
Interrupt request register 1
INT0 interrupt request bit
INT1 interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 2/INT3 interrupt request bit
Timer 3/INT4 interrupt request bit
Interrupt control register 1
INT0 interrupt enable bit
INT1 interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 2/INT3 interrupt enable bit
Timer 3/INT4 interrupt enable bit
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C16)
(ICON1 : address 003E16)
Interrupt request register 2
CNTR0 interrupt request bit
CNTR1 interrupt request bit
Serial I/O2 interrupt request bit
Timer 1/INT2 interrupt request bit
Timer A interrupt request bit
Timer B interrupt request bit
ADT/AD conversion interrupt request bit
Not used (returns "0" when read)
(IREQ2 : address 003D16)
Interrupt control register 2
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
Serial I/O2 interrupt enable bit
Timer 1/INT2 interrupt enable bit
Timer A interrupt enable bit
Timer B interrupt enable bit
ADT/AD conversion interrupt enable bit
Not used (returns "0" when read)
(Do not write "1" to this bit)
0 : Interrupt disabled
1 : Interrupt enabled
(ICON2 : address 003F16)
0 : INT interrupt selected
1 : Timer interrupt selected
Interrupt disable flag I
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
Fig. 13. Interrupt control
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