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參數(shù)資料
| 型號： | M38049FFHFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 97/116頁 |
| 文件大小： | 1261K |
| 代理商： | M38049FFHFP |
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Rev.1.01
Jan 25, 2005
page 81 of 114
REJ03B0131-0101Z
3804 Group (Spec. H)
qOutline Performance
CPU rewrite mode is usable in the single-chip or Boot mode. The
only User ROM area can be rewritten.
In CPU rewrite mode, the CPU erases, programs and reads the in-
ternal flash memory as instructed by software commands. This
rewrite control program must be transferred to internal RAM area
before it can be executed.
The MCU enters CPU rewrite mode by setting “1” to the CPU re-
write mode select bit (bit 1 of address 0FE016). Then, software
commands can be accepted.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or
in error can be verified by reading the status register.
Figure 78 shows the flash memory control register 0.
Bit 0 of the flash memory control register 0 is the RY/BY status
flag used exclusively to read the operating status of the flash
memory. During programming and erase operations, it is “0”
(busy). Otherwise, it is “1” (ready).
Bit 1 of the flash memory control register 0 is the CPU rewrite
mode select bit. When this bit is set to “1”, the MCU enters CPU
rewrite mode. And then, software commands can be accepted. In
CPU rewrite mode, the CPU becomes unable to access the inter-
nal flash memory directly. Therefore, use the control program in
the internal RAM for write to bit 1. To set this bit 1 to “1”, it is nec-
essary to write “0” and then write “1” in succession to bit 1. The bit
can be set to “0” by only writing “0”.
Bit 2 of the flash memory control register 0 is the 8 KB user block
E/W enable bit. By setting combination of bit 4 of the flash memory
control register 2 and this bit as shown in Table 14, E/W is dis-
abled to user block in the CPU rewriting mode.
Bit 3 of the flash memory control register 0 is the flash memory re-
set bit used to reset the control circuit of internal flash memory.
This bit is used when flash memory access has failed. When the
CPU rewrite mode select bit is “1”, setting “1” for this bit resets the
control circuit. To release the reset, it is necessary to set this bit to
“0”.
Bit 5 of the flash memory control register 0 is the User ROM area
select bit and is valid only in the boot mode. Setting this bit to “1”
in the boot mode switches an accessible area from the boot ROM
area to the user ROM area. To use the CPU rewrite mode in the
boot mode, set this bit to “1”. To rewrite bit 5, execute the user-
original reprogramming control software transferred to the internal
RAM in advance.
Bit 6 of the flash memory control register 0 is the program status
flag. This bit is set to “1” when writing to flash memory is failed.
When program error occurs, the block cannot be used.
Bit 7 of the flash memory control register 0 is the erase status flag.
This bit is set to “1” when erasing flash memory is failed. When
erase error occurs, the block cannot be used.
Figure 79 shows the flash memory control register 1.
Bit 0 of the flash memory control register 1 is the Erase suspend
enable bit. By setting this bit to “1”, the erase suspend mode to
suspend erase processing temporaly when block erase command
is executed can be used. In order to set this bit to “1”, writing “0”
and “1” in succession to bit 0. In order to set this bit to “0”, write “0”
only to bit 0.
Bit 1 of the flash memory control register 1 is the erase suspend
request bit. By setting this bit to “1” when erase suspend enable
bit is “1”, the erase processing is suspended.
Bit 6 of the flash memory control register 1 is the erase suspend
flag. This bit is cleared to “0” at the flash erasing.
Fig. 78 Structure of flash memory control register 0
Fig. 79 Structure of flash memory control register 1
b7
b0
Flash memory control register 0
(FMCR0: address : 0FE016: initial value: 0116)
RY/BY
status flag
0 : Busy (being written or erased)
1 : Ready
CPU rewrite mode select bit (Note 1)
0 :
CPU rewrite mode invalid
1 :
CPU rewrite mode valid
8KB user block E/W enable bit
(Notes 1, 2)
0 : E/W disabled
1 : E/W enabled
Flash memory reset bit
(Notes 3, 4)
0 : Normal operation
1 : reset
Not used (do not write “1” to this bit.)
User ROM area select bit
(Note 5)
0 : Boot ROM area is accessed
1 : User ROM area is accessed
Program status flag
0: Pass
1: Error
Erase status flag
0: Pass
1: Error
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
2: This bit can be written only when CPU rewrite mode select bit is “1”.
3: Effective only when the CPU rewrite mode select bit = “1”. Fix this
bit to “0” when the CPU rewrite mode select bit is “0”.
4: When setting this bit to “1” (when the control circuit of flash memory
is reset), the flash memory cannot be accessed for 10
s.
5: Write to this bit in program on RAM
Notes 1: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession. For this bit to be set to “0”, write “0” only to
this bit.
2: Effective only when the suspend enable bit = “1”.
b7
b0
Erase Suspend enble bit (Notes 1)
0 : Suspend invalid
1 : Suspend valid
Erase Suspend
request bit (Notes 2)
0 : Erase restart
1 : Suspend request
Erase Suspend flag
0 :
Erase active
1 :
Erase inactive (Erase Suspend mode)
Not used (do not write “1” to this bit.)
Flash memory control register 1
(FMCR1: address : 0FE116: initial value: 4016)
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