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參數(shù)資料
| 型號(hào)： | M38049FFHFP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 79/116頁(yè) |
| 文件大?。?/td> | 1261K |
| 代理商： | M38049FFHFP |
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Rev.1.01
Jan 25, 2005
page 65 of 114
REJ03B0131-0101Z
3804 Group (Spec. H)
START Condition Generating Method
When writing “1” to the MST, TRX, and BB bits of the I2C status
register (S1: address 001316) at the same time after writing the
slave address to the I2C data shift register (S0: address 001116)
with the condition in which the ES0 bit of the I2C control register
(S1D: address 001416) is “1” and the BB flag is “0”, a START con-
dition occurs. After that, the bit counter becomes “0002” and an
SCL for 1 byte is output. The START condition generating timing is
different in the standard clock mode and the high-speed clock
mode. Refer to Figure 62, the START condition generating timing
diagram, and Table 9, the START condition generating timing
table.
STOP Condition Generating Method
When the ES0 bit of the I2C control register (S1D: address
001416) is “1,” write “1” to the MST and TRX bits, and write “0” to
the BB bit of the I2C status register (S1: address 001316) simulta-
neously. Then a STOP condition occurs. The STOP condition
generating timing is different in the standard clock mode and the
high-speed clock mode. Refer to Figure 63, the STOP condition
generating timing diagram, and Table 10, the STOP condition gen-
erating timing table.
Fig. 62 START condition generating timing diagram
Fig. 63 STOP condition generating timing diagram
Table 10 STOP condition generating timing table
Item
Setup time
Hold time
Standard clock mode
5.0
s (20 cycles)
4.5
s (18 cycles)
Note: Absolute time at
φ = 4 MHz. The value in parentheses denotes the
number of
φ cycles.
High-speed clock mode
3.0
s (12 cycles)
2.5
s (10 cycles)
Table 9 START condition generating timing table
Item
Setup time
Hold time
Standard clock mode
5.0
s (20 cycles)
5.0
s (20 cycles)
Note: Absolute time at
φ = 4 MHz. The value in parentheses denotes the
number of
φ cycles.
High-speed clock mode
2.5
s (10 cycles)
2.5
s (10 cycles)
I2C status register
write signal
Hold time
Setup
time
SCL
SDA
I2C status register
write signal
Hold time
Setup
time
SCL
SDA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M38049FFLHP#U0 | 制造商:Renesas Electronics Corporation 功能描述: |
| M38049RLSS | 功能描述:DEV EMULATOR CHIP RAM 2KB 64SDIP RoHS:否 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 內(nèi)電路編程器、仿真器以及調(diào)試器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 19/Jul/2010 標(biāo)準(zhǔn)包裝:1 系列:* 類(lèi)型:* 適用于相關(guān)產(chǎn)品:* 所含物品:* |
| M3806 | 功能描述:電纜固定件和配件 LTSCG 625 BLACK RoHS:否 制造商:Heyco 類(lèi)型:Cable Grips, Liquid Tight 材料:Nylon 顏色:Black 安裝方法:Cable 最大光束直徑:11.4 mm 抗拉強(qiáng)度: |
| M3806 BK001 | 制造商:Alpha Wire Company 功能描述:CBL 8COND 18AWG BLK 1000' |
| M3806 BK002 | 制造商:Alpha Wire Company 功能描述:CBL 8COND 18AWG BLK 500' |
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