參數(shù)資料
型號： M38039MFH-XXXWG
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PBGA64
封裝： 6 X 6 MM, 0.65 MM PITCH, PLASTIC, FLGA-64
文件頁數(shù)： 20/119頁
文件大?。?/td> 1818K
代理商： M38039MFH-XXXWG
(1/3)
REVISION HISTORY
3803 Group (Spec.H) Data Sheet
Rev.
Date
Description
Page
Summary
First edition issued
Delete the following :“*:KP package is under development.”
Table 4 pin description
VCC,VSS Apply voltage of 2.7–5.5V
→ 1.8V–5.5V
Fig.5 Memory expansion plan
As of Dec. 2002
→ As of Mar. 2003
Notes
(address 3A16)
→ (address 003A16), (address 2316) → (address 002316),
(address 2A16)
→ (address 002A16), (address 3916) → (address 003916)
Fig.61 System clock generating circuit block diagram
Table 10 Recommended operating conditions
Add : VIL “L” input voltage XIN, XCIN 1.8
≤VCC≤5.5V Min. → 0
Table 11 Recommended operating conditions
f(XIN) High-speed mode f(
φ)=f(XIN)/2 2.2≤VCC≤4.0V → 2.7≤VCC≤4.0V
Table 16 A/D converter characteristics
VCC 8bit A/D mode, 10bit A/D mode Max. 5.0
→ 5.5
Table 17 D/A converter characteristics
VCC = 4.0 to 5.5V
→ 4.0≤VCC≤5.5V, VCC = 2.7 to 4.0V → 2.7≤VCC<4.0V
Table 16 A/D converter characteristics, Table 17 D/A converter characteristics
Resolution Unit Bits
→ bit
Table 18 Timing requirements (1) (In high-speed mode)
tC(XIN) Main clock XIN input cycle time 2.7
≤VCC<4.0
Min. 2.6
103/(82VCC-3) → 26103/(82VCC-3)
Table 18 Timing requirements (1) (In high-speed mode),
Table 20 Timing requirements (3) (In middle-speed mode)
tWH(XCIN) Sub-clock input “H” pulse width
→ Sub-clock XCIN input “H” pulse width
tWL(XCIN) Sub-clock input “L” pulse width
→ Sub-clock XCIN input “L” pulse width
Table 19 Timing requirements (2) (In high-speed mode),
Table 20 Timing requirements (4) (In middle-speed mode)
tCL(SCLK2)
→ tWL(SCLK2)
Fig.63 Timing diagram (in single-chip mode)
Delete the following underline parts :
SCLK1 SCLK2 SCLK3 tf , tr
TXD1 TXD3 SOUT2 td(SCLK1-TXD1), td(SCLK2-SOUT2), td(SCLK3-TXD3)
tv(SCLK1-TXD1), tv(SCLK2-SOUT2), tv(SCLK3-TXD3)
–
1,2,6,7
5
7
23
64
68
69
73
75
75,77
76,78
79
STP instruction
Timing
φ (internal clock)
S
R
Q
Middle-speed mode
High-speed or
low-speed mode
Main clock division ratio
selection bits (Note 1)
Prescaler 12
Timer 1
Reset or
STP instruction
(Note 2)
Divider
(Note 3)
FF16
0116
STP instruction
Timing
φ (internal clock)
S
R
Q
Middle-speed mode
High-speed or
low-speed mode
Main clock division ratio
selection bits (Note 1)
Prescaler 12
Timer 1
Reset or
STP instruction
(Note 2)
Divider
(Note 3)
Reset
1.00 Sep. 3, 2001
2.00 May. 28, 2003
3.00 Oct. 14, 2003
3.01 Jun.25, 2004
Flash memory version is added.
6
15
16
Table 5 Pin description is partly revised.
Figure 11 Memory map of special function register (SFR) is partly revised.
Table 8 I/O port function is partly revised.
REVISION HISTORY
相關(guān)PDF資料
PDF描述
M38037M6H-XXXSP 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PDIP64
M38039FFHHP 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PQFP64
M38039MCH-XXXKP 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQFP64
M38034M4H-XXXHP 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQFP64
M38034M4H-XXXSP 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PDIP64
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M38049FFFP#U0 制造商:Renesas Electronics Corporation 功能描述:
M38049FFLHP#U0 制造商:Renesas Electronics Corporation 功能描述:
M38049RLSS 功能描述:DEV EMULATOR CHIP RAM 2KB 64SDIP RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 內(nèi)電路編程器、仿真器以及調(diào)試器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 19/Jul/2010 標(biāo)準(zhǔn)包裝:1 系列:* 類型:* 適用于相關(guān)產(chǎn)品:* 所含物品:*
M3806 功能描述:電纜固定件和配件 LTSCG 625 BLACK RoHS:否 制造商:Heyco 類型:Cable Grips, Liquid Tight 材料:Nylon 顏色:Black 安裝方法:Cable 最大光束直徑:11.4 mm 抗拉強(qiáng)度:
M3806 BK001 制造商:Alpha Wire Company 功能描述:CBL 8COND 18AWG BLK 1000'
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*