參數(shù)資料
型號(hào)： M38039GCH-XXXKP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁(yè)數(shù)： 87/103頁(yè)
文件大?。?/td> 1412K
代理商： M38039GCH-XXXKP
REJ03B0166-0113 Rev.1.13
Aug 21, 2009
Page 84 of 100
3803 Group (Spec.H QzROM version)
2. Notes when selecting clock asynchronous serial I/O
(1) Stop of transmission operation
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial I/Oi
enable bit (i = 1, 3) to “0”.
<Reason>
This is the same as (1) in 1.
(2) Stop of receive operation
Clear the receive enable bit to “0” (receive disabled).
(3) Stop of transmit/receive operation
Only transmission operation is stopped.
Clear the transmit enable bit to “0” (transmit disabled). The
transmission operation does not stop by clearing the serial I/Oi
enable bit (i = 1, 3) to “0”.
<Reason>
This is the same as (1) in 1.
Only receive operation is stopped.
Clear the receive enable bit to “0” (receive disabled).
3. SRDYi (i = 1, 3) output of reception side
When signals are output from the SRDYi pin on the reception side
by using an external clock in the clock synchronous serial I/O
mode, set all of the receive enable bit, the SRDYi output enable
bit, and the transmit enable bit to “1” (transmit enabled).
4. Setting serial I/Oi (i = 1, 3) control register again
Set the serial I/Oi control register again after the transmission
and the reception circuits are reset by clearing both the transmit
enable bit and the receive enable bit to “0.”
Fig 82. Sequence of setting serial I/Oi (i = 1, 3) control
register again
5. Data transmission control with referring to transmit
shift register completion flag
After the transmit data is written to the transmit buffer register,
the transmit shift register completion flag changes from “1” to
“0” with a delay of 0.5 to 1.5 shift clocks. When data
transmission is controlled with referring to the flag after writing
the data to the transmit buffer register, note the delay.
6. Transmission control when external clock is selected
When an external clock is used as the synchronous clock for data
transmission, set the transmit enable bit to “1” at “H” of the
SCLKi (i = 1, 3) input level. Also, write the transmit data to the
transmit buffer register at “H” of the SCLKi input level.
7. Transmit interrupt request when transmit enable bit
is set
When using the transmit interrupt, take the following sequence.
(1) Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to
“0” (disabled).
(2) Set the transmit enable bit to “1”.
(3) Set the serial I/Oi transmit interrupt request bit (i = 1, 3) to
“0” after 1 or more instruction has executed.
(4) Set the serial I/Oi transmit interrupt enable bit (i = 1, 3) to
“1” (enabled).
<Reason>
When the transmission enable bit is set to “1”, the transmit buffer
empty flag and transmit shift register shift completion flag are
also set to “1”.
Therefore, regardless of selecting which timing for the
generating of transmit interrupts, the interrupt request is
generated and the transmit interrupt request bit is set at this point.
8. Writing to baud rate generator i (BRGi) (i = 1, 3)
Write data to the baud rate generator i (BRGi) (i = 1, 3) while the
transmission/reception operation is stopped.
Notes on PWM
The PWM starts from “H” level after the PWM enable bit is set
to enable and “L” level is temporarily output from the PWM pin.
The length of this “L” level output is as follows:
n + 1
2
× f(XIN)
(s)
(Count source selection bit = “0”,
where n is the value set in the prescaler)
n + 1
f(XIN)
(s)
(Count source selection bit = “1”,
where n is the value set in the prescaler)
Notes on A/D Converter
1. Analog input pin
Make the signal source impedance for analog input low, or equip
an analog input pin with an external capacitor of 0.01
F to 1 F.
Further, be sure to verify the operation of application products on
the user side.
<Reason>
An analog input pin includes the capacitor for analog voltage
comparison. Accordingly, when signals from signal source with
high impedance are input to an analog input pin, charge and
discharge noise generates. This may cause the A/D conversion
precision to be worse.
2. A/D converter power source pin
The AVSS pin is A/D converter power source pins. Regardless of
using the A/D conversion function or not, connect it as following:
AVSS: Connect to the VSS line
<Reason>
If the AVSS pin is opened, the microcomputer may have a failure
because of noise or others.
Can be set with the
LDM instruction at
the same time
Set the bits 0 to 3 and bit 6 of the serial I/Oi
control register
Clear both the transmit enable bit (TE) and
the receive enable bit (RE) to “0”
Set both the transmit enable bit (TE) and the
receive enable bit (RE), or one of them to “1”
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