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參數(shù)資料
| 型號： | M38039GCH-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 63/103頁 |
| 文件大?。?/td> | 1412K |
| 代理商： | M38039GCH-XXXHP |
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REJ03B0166-0113 Rev.1.13
Aug 21, 2009
Page 62 of 100
3803 Group (Spec.H QzROM version)
A/D CONVERTER
[AD Conversion Register 1, 2] AD1, AD2
The AD conversion register is a read-only register that stores the
result of an A/D conversion. When reading this register during an
A/D conversion, the previous conversion result is read.
Bit 7 of the AD conversion register 2 is the conversion mode
selection bit. When this bit is set to “0”, the A/D converter
becomes the 10-bit A/D mode. When this bit is set to “1”, that
becomes the 8-bit A/D mode. The conversion result of the 8-bit
A/D mode is stored in the AD conversion register 1. As for 10-bit
A/D mode, not only 10-bit reading but also only high-order 8-bit
reading of conversion result can be performed by selecting the
reading procedure of the AD conversion registers 1, 2 after A/D
conversion is completed (in Figure 55).
As for 10-bit A/D mode, the 8-bit reading inclined to MSB is
performed when reading the AD converter register 1 after A/D
conversion is started; and when the AD converter register 1 is
read after reading the AD converter register 2, the 8-bit reading
inclined to LSB is performed.
[AD/DA Control Register] ADCON
The AD/DA control register controls the A/D conversion
process. Bits 0 to 2 and bit 4 select a specific analog input pin.
Bit 3 signals the completion of an A/D conversion. The value of
this bit remains at “0” during an A/D conversion, and changes to
“1” when an A/D conversion ends. Writing “0” to this bit starts
the A/D conversion.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between
AVSS and VREF into 1024, and that outputs the comparison
voltage in the 10-bit A/D mode (256 division in 8-bit A/D mode).
The A/D converter successively compares the comparison
voltage Vref in each mode, dividing the VREF voltage (see
below), with the input voltage.
10-bit A/D mode (10-bit reading)
Vref =
× n (n = 0
1023)
10-bit A/D mode (8-bit reading)
Vref =
× n (n = 0
255)
8-bit A/D mode
Vref =
× n (n
0.5) (n = 1 255)
=0
(n = 0)
[Channel Selector]
The channel selector selects one of ports P67/AN7 to P60/AN0 or
P07/AN15 to P00/AN8, and inputs the voltage to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input
voltage with the comparison voltage, and then stores the result in
the AD conversion registers 1, 2. When an A/D conversion is
completed, the control circuit sets the AD conversion completion
bit and the AD converter/Serial I/O3 transmit interrupt request
bit to “1”.
Note that because the comparator consists of a capacitor
coupling, set f(XIN) to 500 kHz or more during an A/D
conversion.
Fig 53. Structure of AD/DA control register
Fig 54. Structure of AD conversion register 2
Fig 55. Structure of 10-bit A/D mode reading
VREF
1024
-------------
VREF
256
-------------
VREF
256
-------------
AD/DA control register
(ADCON : address 003416)
Analog input pin selection bits 1
0 0 0: P60/AN0or P00/AN8
0 0 1: P61/AN1or P01/AN9
0 1 0: P62/AN2or P02/AN10
0 1 1: P63/AN3or P03/AN11
1 0 0: P64/AN4or P04/AN12
1 0 1: P65/AN5or P05/AN13
1 1 0: P66/AN6or P06/AN14
1 1 1: P67/AN7or P07/AN15
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
Analog input pin selection bit 2
0: AN0 to AN7 side
1: AN8 to AN15 side
Not used (returns “0” when read)
DA1 output enable bit
0: DA1 output disabled
1: DA1 output enabled
DA2 output enable bit
0: DA2 output disabled
1: DA2 output enabled
b7
b0
b2 b1 b0
0
b7
b0
b8
AD conversion register 2 (AD2)
(AD2: address 003816)
b9
Conversion mode selection bit
0: 10-bit A/D conversion mode
1: 8-bit A/D conversion mode
Not used (returns “0” when read)
10-bit reading
(Read address 003816 before 003516)
AD conversion register 2
(AD2: address 003816)
AD conversion register 1
(AD1: address 003516)
Note : Bits 2 to 6 of address 003816 become “0” at reading.
8-bit reading
(Read only address 003516)
AD conversion register 1
(AD1: address 003516)
b9
b7
b0
b8 b7 b6 b5 b4 b3 b2
b7
b0
b9 b8
b7
b0
b6 b5 b4 b3 b2 b1 b0
0
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