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參數(shù)資料
| 型號： | M38034M4-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 17/138頁 |
| 文件大?。?/td> | 1887K |
| 代理商： | M38034M4-XXXHP |
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Rev.4.01
Nov 14, 2003
page 111 of 136
3803/3804 Group
q CPU reprogramming mode operation procedure
The operation procedure in CPU reprogramming mode is de-
scribed below.
< Beginning procedure >
Apply 0 V to the CNVss/VPP pin for reset release.
Set the CPU mode register (see Figure 103).
After CPU reprogramming mode control program is transferred to
internal RAM, jump to this control program on RAM. (The follow-
ing operations are controlled by this control program).
Set “1" to the CPU reprogramming mode select bit.
Apply VPPH to the CNVSS/VPP pin.
Wait till CNVSS/VPP pin becomes 12V.
Read the CPU reprogramming mode monitor flag to confirm
whether the CPU reprogramming mode is valid.
The operation of the flash memory is executed by software-com-
mand-writing to the flash command register .
Note: The following are necessary other than this:
Control for data which is input from the external (serial I/O
etc.) and to be programmed to the flash memory
Initial setting for ports etc.
Writing to the watchdog timer
< Release procedure >
Apply 0 V to the CNVSS/VPP pin.
Wait till CNVSS/VPP pin becomes 0 V.
Set the CPU reprogramming mode select bit to “0.”
Each software command is explained as follows.
q Read command
When “0016" is written to the flash command register, the 3803/
3804 group enters the read mode. The contents of the corre-
sponding address can be read by reading the flash memory (For
instance, with the LDA instruction etc.) under this condition.
The read mode is maintained until another command code is written
to the flash command register. Accordingly, after setting the read
mode once, the contents of the flash memory can continuously be
read.
After reset and after the reset command is executed, the read
mode is set.
Fig. 102 Flash command register bit configuration
Fig. 103 CPU mode register bit configuration in CPU rewriting
mode
Writing of software command
<Command code>
“0016”
“4016”
“C016”
“2016” + “2016”
“A016”
“FF16” + “FF16”
<Software command name>
Read command
Program command
Program verify command
Erase command
Erase verify command
Reset command
Note: The flash command register is write-only register.
Flash command register
(FCMD : address 0FFF16)
76
5
4
3
2
1
0
Processor mode bits
b1 b0
0
0 : Single-chip mode
0
1 : Not available
1
X : Not available
Port XC switch bit
0 : I/O port function (stop oscillating)
1 : XCIN–XCOUT oscillating function
Main clock (XIN–XOUT) stop bit
0 : Oscillating
1 : Stopped
Main clock division ratio selection bits
b7 b6
0
0 :
φ = f(XIN)/2 (high-speed mode)
0
1 :
φ = f(XIN)/8 (middle-speed mode)
1
0 :
φ = f(XCIN)/2 (low-speed mode)
1
1 : Not available
00
1
CPU mode register
(CPUM : address 003B16)
b7
b0
Stack page selection bit
0 : 0 page
1 : 1 page
Fix this bit to “1”.
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