參數(shù)資料
型號(hào)： M38034M4-XXXHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8.4 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 10/138頁
文件大?。?/td> 1887K
代理商： M38034M4-XXXHP
Rev.4.01
Nov 14, 2003
page 105 of 136
3803/3804 Group
Functional Outline (serial I/O mode)
In the serial I/O mode, data is transferred synchronously with the
clock using serial input/output. The input data is read from the
SDA pin into the internal circuit synchronously with the rising edge
of the serial clock pulse; the output data is output from the SDA
pin synchronously with the falling edge of the serial clock pulse.
Data is transferred in units of eight bits.
In the first transfer, the user inputs the command code. This is fol-
lowed by address input and data input/output according to the
contents of the command. Table 24 shows the software com-
mands used in the serial I/O mode. The following explains each
software command.
Table 24 Software command (serial I/O mode)
Read
Program
Program verify
Erase
Erase verify
Error check
Number of transfers
Command
First command
code input
0016
4016
C016
2016
A016
8016
Read address L (Input)
Program address L (Input)
Verify data (Output)
2016 (Input)
Verify address L (Input)
Error code (Output)
Second
Read address H (Input)
Program address H (Input)
—————
Verify address H (Input)
—————
Third
Fourth
Read data (Output)
Program data (Input)
—————
Verify data (Output)
—————
q Read command
Input command code 0016 in the first transfer. Proceed and input
the low-order 8 bits and the high-order 8 bits of the address and
__
pull the OE pin low. When this is done, the 3803/3804 group reads
out the contents of the specified address, and then latchs it into
__
the internal data latch. When the OE pin is released back high and
serial clock is input to the SCLK pin, the read data that has been
latched into the data latch is serially output from the SDA pin.
Fig. 95 Timings during reading
“L”
SCLK
BUSY
OE
SDA
tCH
A0
A7
A8
A15
D0
D7
tCH
tCR
Command code input (0016)
Read address input (L)
Read address input (H)
Read data output
tWR
Read
tRC
Note : When outputting the read data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
00000000
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