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參數(shù)資料
| 型號： | M38030F2L-XXXWG |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 30/119頁 |
| 文件大小： | 1575K |
| 代理商： | M38030F2L-XXXWG |
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Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 30 of 117
3803 Group (Spec.L)
TIMERS
8-bit Timers
The 3803 group (Spec.L) has four 8-bit timers: timer 1, timer 2,
timer X, and timer Y.
The timer 1 and timer 2 use one prescaler in common, and the
timer X and timer Y use each prescaler. Those are 8-bit
prescalers. Each of the timers and prescalers has a timer latch or
a prescaler latch.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are down-counters. When the timer reaches “00
16
”, an
underflow occurs at the next count pulse and the contents of the
corresponding timer latch are reloaded into the timer and the
count is continued. When the timer underflows, the interrupt
request bit corresponding to that timer is set to “1”.
Timer divider
The divider count source is switched by the main clock division
ratio selection bits of CPU mode register (bits 7 and 6 at address
003B
16
). When these bits are “00” (high-speed mode) or “01”
(middle-speed mode), X
IN
is selected. When these bits are “10”
(low-speed mode), X
CIN
is selected.
Prescaler 12
The prescaler 12 counts the output of the timer divider. The
count source is selected by the timer 12, X count source selection
register among 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512, 1/1024 of f(X
IN
) or f(X
CIN
).
Timer 1 and Timer 2
The timer 1 and timer 2 counts the output of prescaler 12 and
periodically set the interrupt request bit.
Prescaler X and prescaler Y
The prescaler X and prescaler Y count the output of the timer
divider or f(X
CIN
). The count source is selected by the timer 12,
X count source selection register (address 000E
16
) and the timer
Y, Z count source selection register (address 000F
16
) among 1/2,
1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, 1/512, and 1/1024 of
f(X
IN
) or f(X
CIN
); and f(X
CIN
).
Timer X and Timer Y
The timer X and timer Y can each select one of four operating
modes by setting the timer XY mode register (address 0023
16
).
(1) Timer mode
Mode selection
This mode can be selected by setting “00” to the timer X
operating mode bits (bits 1 and 0) and the timer Y operating
mode bits (bits 5 and 4) of the timer XY mode register (address
0023
16
).
Explanation of operation
The timer count operation is started by setting “0” to the timer X
count stop bit (bit 3) and the timer Y count stop bit (bit 7) of the
timer XY mode register (address 0023
16
).
When the timer reaches “00
16
”, an underflow occurs at the next
count pulse and the contents of timer latch are reloaded into the
timer and the count is continued.
(2) Pulse Output Mode
Mode selection
This mode can be selected by setting “01” to the timer X
operating mode bits (bits 1 and 0) and the timer Y operating
mode bits (bits 5 and 4) of the timer XY mode register (address
0023
16
).
Explanation of operation
The operation is the same as the timer mode’s. Moreover the
pulse which is inverted each time the timer underflows is output
from CNTR
0
/CNTR
1
pin. Regardless of the timer counting or
not the output of CNTR
0
/CNTR
1
pin is initialized to the level of
specified by their active edge switch bits when writing to the
timer. When the CNTR
0
active edge switch bit (bit 2) and the
CNTR
1
active edge switch bit (bit 6) of the timer XY mode
register (address 0023
16
) is “0”, the output starts with “H” level.
When it is “1”, the output starts with “L” level.
Switching the CNTR
0
or CNTR
1
active edge switch bit will
reverse the output level of the corresponding CNTR
0
or CNTR
1
pin.
Precautions
Set the double-function port of CNTR
0
/CNTR
1
pin and port
P5
4
/P5
5
to output in this mode.
(3) Event Counter Mode
Mode selection
This mode can be selected by setting “10” to the timer X
operating mode bits (bits 1 and 0) and the timer Y operating
mode bits (bits 5 and 4) of the timer XY mode register (address
0023
16
).
Explanation of operation
The operation is the same as the timer mode’s except that the
timer counts signals input from the CNTR
0
or CNTR
1
pin. The
valid edge for the count operation depends on the CNTR
0
active
edge switch bit (bit 2) or the CNTR
1
active edge switch bit (bit 6)
of the timer XY mode register (address 0023
16
). When it is “0”,
the rising edge is valid. When it is “1”, the falling edge is valid.
Precautions
Set the double-function port of CNTR
0
/CNTR
1
pin and port
P5
4
/P5
5
to input in this mode.
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