參數(shù)資料
型號(hào)： M38006M2-XXXSP
廠商： Mitsubishi Electric Corporation
元件分類： DC/DC變換器
英文描述： 1 watt dc-dc converters
中文描述： 1瓦的DC - DC轉(zhuǎn)換器
文件頁數(shù)： 160/173頁
文件大小： 4203K
代理商： M38006M2-XXXSP
APPENDIX
3.9 Machine instructions
3-58
3800 GROUP USER’S MANUAL
Addressing mode
Symbol
Function
Details
IMP
IMM
A
BIT, A
ZP
BIT, ZP
OP n
# OP n
# OP n
# OP n
# OP n
#
OP n
#
Branches when the contents of overflow flag is
“0”.
Branches when the contents of overflow flag is
“1”.
Clears the contents of the bit specified in the
accumulator or memory to “0”.
Clears the contents of the carry flag to “0”.
Clears the contents of decimal mode flag to
“0”.
Clears the contents of interrupt disable flag to
“0”.
Clears the contents of index X mode flag to
“0”.
Clears the contents of overflow flag to “0”.
Compares the contents of accumulator and
memory.
Compares the contents of the memory speci-
fied by the addressing mode with the contents
of the address indicated by index register X.
Forms a one’s complement of the contents of
memory, and stores it into memory.
Compares the contents of index register X and
memory.
Compares the contents of index register Y and
memory.
Decrements the contents of the accumulator
or memory by 1.
Decrements the contents of index register X
by 1.
Decrements the contents of index register Y
by 1.
Divides the 16-bit data that is the contents of
M (zz + x + 1) for high byte and the contents of
M (zz + x) for low byte by the accumulator.
Stores the quotient in the accumulator and the
1’s complement of the remainder on the stack.
“Exclusive-ORs” the contents of accumulator
and memory. The results are stored in the ac-
cumulator.
“Exclusive-ORs” the contents of the memory
specified by the addressing mode and the
contents of the memory at the address indi-
cated by index register X. The results are
stored into the memory at the address indi-
cated by index register X.
Increments the contents of accumulator or
memory by 1.
Increments the contents of index register X by
1.
Increments the contents of index register Y by
1.
BVC
(Note 4)
BVS
(Note 4)
CLB
CLC
CLD
CLI
CLT
CLV
CMP
(Note 3)
COM
CPX
CPY
DEC
DEX
DEY
DIV
EOR
(Note 1)
INC
INX
INY
V = 0
V = 1
Ab or Mb
←
0
C
←
0
D
←
0
I
←
0
T
←
0
V
←
0
When T = 0
A – M
When T = 1
M(X) – M
M
←
M
X – M
Y – M
A
←
A – 1 or
M
←
M – 1
X
←
X – 1
Y
←
Y – 1
A
←
(M(zz + X + 1),
M(zz + X)) / A
M(S)
←
1’s complememt
of Remainder
S
←
S – 1
When T = 0
A
←
A V M
When T = 1
M(X)
←
M(X) V M
A
←
A + 1 or
M
←
M + 1
X
←
X + 1
Y
←
Y + 1
18
D8
58
12
B8
CA
88
E8
C8
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
C9
E0
C0
49
2
2
2
2
2
2
2
2
1A
3A
2
2
1
1
1B
+
2i
C5
44
E4
C4
C6
45
E6
3
5
3
3
5
3
5
2
2
2
2
2
2
2
1F
+
2i
2
1
5
2
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