參數(shù)資料
型號: M38005S5-XXXSP
廠商: Mitsubishi Electric Corporation
元件分類: 串行ADC
英文描述: 8-Bit 41 kSPS ADC Serial Out, Ratiometric Op or Vcc Ref, TTL/MOS Input & Output Compatible, 4 Ch. 16-TSSOP 0 to 70
中文描述: 8位單片機
文件頁數(shù): 75/173頁
文件大?。?/td> 4203K
代理商: M38005S5-XXXSP
2-27
3800 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
bit
Timer Y interrupt request bit
Serial I/O receive interrupt
request bit
Serial I/O transmit interrupt
request bit
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
0
0
0
Interrupt request reigster 1 (IREQ1) [Address : 3C
16
]
Name
INT
0
interrupt request bit
INT
1
interrupt request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
6
6
6
6
4
5
6
7
0
0
0
0
Timer 1 interrupt request bit
0 : No interrupt request
1 : Interrupt request
0 : No interrupt request
1 : Interrupt request
Timer 2 interrupt request bit
6
6
6
6
6
“0” is set by software, but not “1.”
Timer X interrupt request
Fig. 2.3.8 Structure of Interrupt request register 1
Fig. 2.3.9 Structure of Interrupt control register 1
Timer Y interrupt enable bit
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0
B
0
Function
At reset
R W
0
1
2
3
0
0
0
Interrupt control register 1 (ICON1) [Address : 3E
16
]
Name
INT
0
interrupt enable bit
INT
1
interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
4
5
6
7
0
0
0
0
Timer X interrupt enable bit
Timer 1 interrupt enable bit
0 : Interrupt disabled
1 : Interrupt enabled
0 : Interrupt disabled
1 : Interrupt enabled
Timer 2 interrupt enable bit
Serial I/O transmit interrupt
enable bit
Serial I/O receive interrupt
enable bit
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