參數(shù)資料
型號： M38005S5-XXXSP
廠商： Mitsubishi Electric Corporation
元件分類： 串行ADC
英文描述： 8-Bit 41 kSPS ADC Serial Out, Ratiometric Op or Vcc Ref, TTL/MOS Input & Output Compatible, 4 Ch. 16-TSSOP 0 to 70
中文描述： 8位單片機(jī)
文件頁數(shù)： 4/173頁
文件大?。?/td> 4203K
代理商： M38005S5-XXXSP
BEFORE USING THIS USER’S MANUAL
This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such
as hardware design or software development. Chapter 3 also includes necessary information for systems development.
Be sure to refer to this chapter.
1. Organization
G
CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer and operation of each peripheral function.
G
CHAPTER 2 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on setting examples
of related registers.
G
CHAPTER 3 APPENDIX
This chapter includes necessary information for systems development using the microcomputer, electric
characteristics, a list of registers, the masking confirmation (mask ROM version), and mark specifications which
are to be submitted when ordering.
2. Structure of register
The figure of each register structure describes its functions, contents at reset, and attributes as follows :
Note 2. Bit attributesThe attributes of control register bits are classified into 3 bytes : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
: Bit in which nothing is arranged
0 1 :
0 : 0 page
Name
Function
At reset
R W
B
0
1
2
3
4
5
6
7
0
0
0
0
0
1
6
b0
b1
b2
b3
b4
b5
0
b6
b7
Contents immediately after reset release
Bit attributes
(Note 1)
Processor mode bits
Stack page selection bit
Nothing arranged for these bits. These are write disabled
bits. When these bits are read out, the contents are “0.”
Fix this bit to “0.”
Main clock (X
IN
-X
OUT
) stop bit
Internal system clock selection bit
0 0 : Single-chip mode
Not available
0 : Operating
IN
-X
OUT
selected
0 : X
CIN
-X
COUT
: Bit that is not used for control of the corresponding function
Note 1. Contents immediately after reset release
0“0” at reset release
1“1” at reset release
UndefinedUndefined or reset release
Contents determined by option at reset release
6
RRead
Read enabled
Read disabled
WWrite
Write enabled
Write disabled
(Note 2)
6
CPU mode register (CPUM) [Address : 3B
16
]
Bits
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