參數(shù)資料
型號: M38002E4FS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CQCC64
封裝: QFN-64
文件頁數(shù): 158/174頁
文件大小: 1752K
代理商: M38002E4FS
2-35
3800 GROUP USER’S MANUAL
APPLICATION
2.3 Serial I/O
Fig. 2.3.18 Control procedure at a receiving side [Communication using a clock synchronous
serial I/O]
RESET
Initialization
SIOCON (Address : 1A16 )
1111X11X2
.....
TB/RB (Address : 1816 )
Dummy data
SRDY
output
SRDY
signal is output by writing data to
the TB/RB.
Using the SRDY , the transmit enabled bit
(bit4) of the SIOCON is set to “1.”
An interval of 2 ms is generated by a timer.
Pass 2 ms?
Y
N
Check a completion of receiving
(Receive buffer full flag)
SIOSTS (Address : 1916 ), bit1?
1
0
Read out reception data from
TB/RB (Address : 1816 )
Receive the first byte data.
A Receive buffer full flag is set to “0” by reading data.
Check a completion of receiving
(Receive buffer full flag)
SIOSTS (Address : 1916 ), bit1?
1
0
Read out reception data from
TB/RB (Address : 1816 )
Receive the second byte data.
A Receive buffer full flag is set to “0” by reading data.
X : This bit is not used in this application.
Set it to “0” or “1.” It’s value can be disregarded.
q
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