參數(shù)資料
型號(hào): M37906M4C-XXXFP
元件分類(lèi): 微控制器/微處理器
英文描述: 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDSO42
封裝: 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42
文件頁(yè)數(shù): 77/101頁(yè)
文件大?。?/td> 766K
代理商: M37906M4C-XXXFP
77
M37906M4C-XXXFP, M37906M4C-XXXSP, M37906M4H-XXXFP
M37906M4H-XXXSP, M37906M6C-XXXFP, M37906M6C-XXXSP
M37906M8C-XXXFP, M37906M8C-XXXSP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
param
etric
lim
its are
subject
to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 86 Bit configuration of particular function select register 0
Fig. 85 Bit configuration of clock control register 0
7
6
543
2
1
0
Clock control register 0
Fix this bit to “1”.
PLL circuit operation enable bit (Note 1)
0: PLL frequency multiplier is inactive, and pin VCONT is invalid (floating state).
1: PLL frequency multiplier is active, and pin VCONT is valid.
PLL multiplication ratio select bits (Note 2)
00: Do not select.
01: Double
10: Triple
11: Quadruple
Fix this bit to “1”.
System clock select bit (Note 3)
0: fXIN
1: fPLL
Peripheral device’s clock select bits 1, 0
See Table 10.
Address
BC16
1
Notes 1: When not using the PLL frequency multiplier, be sure to clear this bit to “0”.
In the stop mode, the PLL circuit stops its operation regardless of this bit’s content; at this
time, pin VCONT is invalid.
2: When rewriting this bit, be sure to clear bit 5 to “0” simultaneously. Also, after this bit is
rewritten, insert a waiting time of 2 ms, and then set bit 5 to “1”.
3: When the PLL circuit operation enable bit (bit 1) has been cleared to “0”, this bit will also
be cleared to “0”. When bit 1 = “0”, nothing can be written to this bit. (Fixed to be “0”.)
7
6
543
2
1
0
Particular function select register 0
External clock input select bit (Note)
0: Oscillation circuit is active. (The oscillator is connected.)
Watchdog timer is used at stop mode termination.
1: Oscillation circuit is inactive. (The externally-generated clock is input.)
When the system clock select bit = “0”,
watchdog timer is not used at stop mode termination.
When the system clock select bit = “1”,
watchdog timer is used at stop mode termination.
Fix this bit to “0”.
STP instruction invalidity select bit (Note)
0: STP instruction is valid.
1: STP instruction is invalid.
Note:
Address
6216
00
0
Writing to these bits requires the following procedure:
Write “5516” to this register. (The bit status does not change only by this writing.)
Succeedingly, write “0” or “1” to each bit.
Also, use the MOVM (MOVMB) instruction or STA (STAB, STAD) instruction
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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