參數(shù)資料
型號: M37905M4C-XXXFP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP64
封裝: 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64
文件頁數(shù): 58/102頁
文件大小: 881K
代理商: M37905M4C-XXXFP
59
M37905M4C-XXXFP, M37905M4C-XXXSP
M37905M6C-XXXFP, M37905M6C-XXXSP
M37905M8C-XXXFP, M37905M8C-XXXSP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 66 Clock synchronous serial I/O timing
Interrupt request at completion of reception
When the RIk flag changes from “0” to “1”, in other words, when the
receive operation is completed, the interrupt request bit of the
UARTk receive interrupt control register can be set to “1”.
The timing when this interrupt request bit is to be set to “1” can be
selected from the following:
Each reception
When an error occurs at reception
If bit 5 of the UARTk transmit/receive control register 0 (UART re-
ceive interrupt mode select bit) is cleared to “0”, the interrupt request
bit is set to “1” at each reception. If bit 5 is set to “1”, the interrupt re-
quest bit is set to “1” only when an error occurs. (In the clock syn-
chronous serial communication, only when an overrun error occurs,
the interrupt request bit is set to “1”.)
Polarity of transfer clock
In the clock synchronous serial communication, by bit 6 of the UARTj
transmit/receive control register 0 (CPL), the polarity of a transfer
clock can be selected.
As shown in Figure 67, when bit 6 = “0”, the polarity is as follows:
In transmission, transmit data is output at the falling edge of CLKj.
In reception, receive data is input at the rising edge of CLKk.
When not in transfer, CLKi is at “H” level.
When bit 6 = “1”, the polarity is as follows:
In transmission, transmit data is output at the rising edge of CLKj.
In reception, receive data is input at the rising edge of CLKk.
When not in transfer, CLKi is at “L” level.
Transmission
clock
TEj
1/fi
× (n + 1) × 2
1/fi
× (n + 1) × 2
TIj
CTSj
Write in transmit buffer register
D0 D1 D2 D3 D4 D5 D6 D7
D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0
Transmit register
←Transmit buffer register
Stopped because TEj = “0”
CLKj
TENDj
TXDj
TXEPTYj
相關(guān)PDF資料
PDF描述
M37905M8C-XXXFP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP64
M37905M8C-XXXSP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP64
M37905M4C-XXXSP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PDIP64
M37905M4C-XXXFP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP64
M37905M8C-XXXFP 16-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP64
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