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參數(shù)資料
| 型號(hào)： | M37753M8C-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | FINE PITCH, QFP-80 |
| 文件頁數(shù)： | 80/109頁 |
| 文件大?。?/td> | 865K |
| 代理商： | M37753M8C-XXXHP |
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MITSUBISHI MICROCOMPUTERS
M37753M8C-XXXFP, M37753M8C-XXXHP
M37753S4CFP, M37753S4CHP
72
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
input while E is “L”.
When the BYTE pin level “H”, port P1 functions as an address output
pin.
Port P2 has two functions depending on the level of the BYTE pin. In
both cases, the I/O port function is lost.
When the BYTE pin level is “L”, port P2 functions as an address out-
put pin while E is “H” and as an even-address-data I/O pin while E is
“L”. However, if an internal memory is read, external data is not input
while E is “L”.
When the BYTE pin level is “H”, port P2 functions as an address out-
put pin while E is “H” and as an even- and odd-address-data I/O pin
while E is “L”. However, if an internal memory is read, external data is
not input while E is “L”.
Ports P30, P31, P32, and P33 become R/W, BHE, ALE, and HLDA
output pins respectively and lose their I/O port functions.
R/W is a read/write signal which indicates a read when it is “H” and a
write when it is “L”.
BHE is a byte-high-enable signal which indicates that an odd ad-
dress is accessed when it is “L”.
Therefore, two bytes at even and odd addresses are accessed si-
multaneously when address A0 is “L” and BHE is “L”.
ALE is an address-latch-enable signal used to latch the address sig-
nal from a multiplexed signal of address and data. The latch is open
while ALE is “H”, so that the address signal passes through; the ad-
dress is held while ALE is “L”.
HLDA is a hold-acknowledge signal and is used to indicate to the
external that the microcomputer accepts HOLD input and enters
Hold state.
Ports P40 and P41 become HOLD and RDY input pins, respectively,
and their I/O port function are lost.
HOLD is a hold-request signal. It is an input signal used to make the
microcomputer enter Hold state. HOLD input is accepted when the
φ BIU has fallen from “H” to “L” level while the bus is not used. Ports
P0, P1, P30 and P31 enter the floating state while the microcomputer
stays in Hold state. These ports enter the floating state one cycle of
φBIU later than HLDA signal becomes “L” level. When terminating Hold
state, these ports are released from the floating state one cycle of
φ BIU later than HLDA signal becomes “H” level.
RDY is a ready signal. When this signal goes “L”,
φ CPU and φ BIU stop
at “L”. RDY is used when a slow external memory is connected, and
so on.
Port P42 becomes a normal I/O port when bit 7 of the processor
mode register 0 is “0” and becomes the clock
φ 1 output pin when bit
7 is “1”. The
φ 1 output is independent of RDY and does not stop even
when
φ CPU and φ BIU stop owing to “L” input to the RDY pin.
Processor modes are explained bellow.
Fig. 86 External memory area for each mode
Microprocessor
mode
Memory expansion
mode
FFFFFF16
ROM
RAM
SFR
8016
216 to 916
The shaded area is the external memory area.
(1) Single-chip mode [00]
The microcomputer enters the single-chip mode by connecting the
CNVss pin to Vss and starting from reset. Ports P0 to P4 all function
as normal I/O ports. Port P42 can output clock source
φ 1 by setting
bit 7 of the processor mode register 0 to “1”. For clock
φ1, refer to Fig-
ure 82.
In this mode, enable signal E is output from pin E. Signal E output
can be stopped by setting the signal output disable select bit (bit 4 of
particular function select register 1) to “1”, and it is possible to switch
the output to “L” level. Table 8 shows the function of the signal output
disable select bit’s function.
(2) Memory expansion mode [01]
The microcomputer enters the memory expansion mode by setting
the processor mode bits to “01” after connecting the CNVss pin to
Vss and starting from reset.
Pin E becomes the E output pin. E is an enable signal and is “L” dur-
ing the data/instruction-code-read or data-write term. When the inter-
nal memory area is read or written, the E can be fixed to “H” by
setting the signal output disable select bit (bit 4 of particular function
select register 1) to “1”.
Port P0 becomes an address output pin, and its I/O port function are
lost.
Port P1 has two functions depending on the level of the BYTE pin. In
both cases, the I/O port function is lost.
When the BYTE pin level is “L”, port P1 functions as an address out-
put pin while E is “H” and as an odd-address-data I/O pin while E is
“L”. However, if an internal memory area is read, external data is not
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37753S4CFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37753S4CHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M37754 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16BIT CMOS MICROCOMPUTER |
| M37754FFCGP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| M37754FFCHP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
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