參數(shù)資料
型號(hào): M37753M8C-XXXHP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 40 MHz, MICROCONTROLLER, PQFP80
封裝: FINE PITCH, QFP-80
文件頁數(shù): 76/109頁
文件大小: 865K
代理商: M37753M8C-XXXHP
69
MITSUBISHI MICROCOMPUTERS
M37753M8C-XXXFP, M37753M8C-XXXHP
M37753S4CFP, M37753S4CHP
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus cycle in WIT/STP
When the WIT/STP instruction is executed with the standby state se-
lect bit 1 (bit 6 of particular function select register 0) = “0”, the clock
sources
φ BIU and φ CPU or oscillation stop without waiting for
completion of the bus cycle being executed. Accordingly, the micro-
computer may enter WIT/STP state during bus access in which out-
put of pin E is “L”.
Otherwise, when the WIT/STP instruction is executed with the
standby state select bit 1 = “1”, the clock sources
φ BIU and φ CPU or
oscillation stop after completion of read or write in the bus access
cycle being executed. Consequently, in WIT/STP state, the bus be-
comes the nonaccess state in which output of pin E is “H”.
Bus state in WIT/STP
Normally, pins for the address output, data input/output and bus
control signal output in the memory expansion/microprocessor mode
(ports P0 to P3 in single-chip mode; refer to section on Processor
mode) retain the state as external bus pins when the clock sources
φ BIU and φ CPU stop in WIT/STP state.
However, when the WIT/STP instruction is executed with the standby
state select bit 0 (bit 5 of particular function select register 0) = “1”,
those pins function depending on the contents of each port direction
register and port latch in WIT/STP state like ports in single-chip
mode. That is, when setting arbitrary data to the port latch and the
contents of direction register to “1”, that data is output from the pin;
when clearing the contents of direction register to “0”, the pin be-
comes floating. This function makes the external bus arbitrary state
in WIT/STP state. When making pins floating, take consideration with
an external circuit to prevent their electric potential from becoming
half level of the electric potential.
When writing to registers relevant to ports P0 to P3 in the memory
expansion/microprocessor mode, set the standby state select bit 0 to
“1” before that write. If that bit is “0”, write is impossible, because
addresses corresponding to registers relevant to ports P0 to P3,
which are addresses 216 to 916 are the external memory areas
shown in Figure 86.
The E pin state can arbitrarily be selected in WIT/STP state in the
memory expansion/microprocessor mode, too. Refer to the Table 8
for details.
Note that the function of arbitrary data output cannot be emulated
using a debugger.
Table 8 Signal output disable select bit function (bit 4 of particular function select register 1; Figure 63)
Processor mode
Pin
Function
Signal output disable select bit = “0”
Outputs enable signal E.
Outputs E when accessing internal/external
memory area.
Outputs “H” or “L” after executing WIT/STP
instruction
Outputs “H” when standby state select bit 1 is
“1”.
Signal output disable select bit = “1”
Outputs “L”.
Outputs E when accessing external memory
area only.
Outputs “H” or “L” after executing WIT/STP
instruction.
Outputs “L” when standby state select bit 1 is
“1” and standby state select bit 0 is “1”.
Outputs “H” when standby state select bit 1 is
“1” and standby state select bit 0 is “0.”
Outputs contents of port P42 latch; necessary
to set its direction register bit to “1”.
Note : All functions of signal output disable select bit cannot be debugged using an debugger.
Memory expansion mode
Microprocessor mode
Outputs clock
φ 1 regardless of φ 1 output
select bit.
E
φ 1
Single-chip mode
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