參數(shù)資料
型號： M37735S4LHP
廠商： Mitsubishi Electric Corporation
英文描述： 16-BIT CMOS MICROCOMPUTER
中文描述： 16位CMOS微機(jī)
文件頁數(shù)： 13/36頁
文件大?。?/td> 935K
代理商： M37735S4LHP
13
MITSUBISHI MICROCOMPUTERS
M37735S4BFP
16-BIT CMOS MICROCOMPUTER
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
CS
0
to
4
are the chip select signals and are “L” when the address
shown in Table 2 is accessed.
RSMP
is the ready-sampling signal
which is output for the
RDY
input described later when the external
RSMP
and
___
____
n
(n = 0 to 4) to the
pin, read/write term for any address areas
can be extended by 1 cycle of clock
term can also be extended by 2 cycles of clock
function and wait 0/1 function specified with the wait bit are used
together.
Pins P1
0
/A
8
/D
8 —
P1
7
/A
15
/D
15
have two functions depending on the
level of the BYTE pin.
When the BYTE pin level is “L”, pins P1
0
/A
8
P1
function
as address (A
8
to A
15
) output pins while
or
WEL
,
WEH
are “H”
and as odd address data I/O pins while these signals are “L”. However,
if an internal memory is read, external data is ignored while
RDE
is
“L”.
When the BYTE pin level is “H”, pins P1
0
/A
8
/D
8 —
P1
7
/A
15
/D
15
function
as address (A
8
to A
15
) output pins.
Pins P2
0
/A
0
/D
0 —
P2
7
/A
7
/D
7
have two functions depending on the
level of the BYTE pin.
When the BYTE pin level is “L”, pins P2
0
/D
0 —
P2
7
/A
7
/D
7
function
as address (A
0
to A
7
) output pins while
or
WEL
,
WEH
are “H” and
as even address data I/O pins while these signals are “L”. However,
if an internal memory is read, external data is ignored while
RDE
is
“L”.
When the BYTE pin level is “H”, pins P2
0
/D
0 —
P2
7
/A
7
/D
7
function
as address (A
0
to A
7
) output pins while
or
WEL
,
WEH
are “H” and
as even and odd address data I/O pins while these signals are “L”.
WEL
,
WEH
are the write-enable low signal and the write-enable high
signal, respectively. These signals are “L” during the data write term
of the write cycle, but their operations differ depending on the BYTE
pin level.
In the case the BYTE pin level is “L”,
is “L” when writing to
an even address,
WEH
is “L” when writing to an odd address, and
both
WEL
and
WEH
are “L” when writing to even and odd addresses.
WEL
is “L”, and
WEH
retains “H”.
WEL
and
WEH
can also be fixed to
“H” when the internal memory is accessed, same as
RDE
, by writing
“1” to the signal output disable selection bit.
ALE is an address latch enable signal used to latch the address signal
from a multiplexed signal of address and data. The latch is transparent
while ALE is “H” to let the address signal pass through and held
____
is a hold acknowledge signal and is used to notify externally
when the microcomputer receives
HOLD
input and enters into hold
HOLD
is a hold request signal. It is an input signal used to put the
microcomputer in hold state.
HOLD
input is accepted when the internal
clock
falls from “H” level to “L” level while the bus is not used.
Pins P0
0
/
CS
0
—
P3
1
/
WEH and
RDE
are floating while the microcomputer
stays in hold state. After
HLDA
signal changes to “L” level and one
passed, these ports become floating. After
____
signal changes to “H” level and one cycle of internal clock
passed, these ports are released from floating state.
___
1
. In addition, the read/write
1
if the above
___
___
___
___
___
RDY
is a ready signal. If this signal goes “L”, the internal clock
stops at “L”.
RDY
is used when slow external memory is attached.
P4
2
/
independent of
RDY
and does not stop even when internal clock
stops because of “L” input to the
RDY
pin.
1
pin is an output pin for clock
1
. The
1
output is
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