參數(shù)資料
型號: M37733M4LXXXHP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù): 8/34頁
文件大小: 446K
代理商: M37733M4LXXXHP
M37733M4LXXXHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
paramentic
limits
are
suject
to change.
13
Limits
Min.
Max.
tc
External clock input cycle time (Note 1)
83
ns
tw(H)
External clock input high-level pulse width (Note 2)
33
ns
tw(L)
External clock input low-level pulse width (Note 2)
33
ns
tr
External clock rise time
15
ns
tf
External clock fall time
15
ns
TIMING REQUIREMENTS (VCC = 2.7 – 5.5 V, VSS = 0 V, Ta = –40 to +85 °C, f(XIN) = 12 MHz, unless otherwise noted (Note 1))
Notes 1. This applies when the main clock division selection bit = “0” and f(f2) = 6 MHZ.
2. Input signal’s rise/fall time must be 100 ns or less, unless otherwise noted.
Unit
Symbol
Parameter
Notes 1. When the main clock division selection bit = “1”, the minimum value of tc = 166 ns.
2. When the main clock division selection bit = “1”, values of tw(H) / tc and tw(L) / tc must be set to values from 0.45 through 0.55.
External clock input
Single-chip mode
Unit
Symbol
Parameter
Limits
Min.
Max.
tsu(P0D–E)
Port P0 input setup time
200
ns
tsu(P1D–E)
Port P1 input setup time
200
ns
tsu(P2D–E)
Port P2 input setup time
200
ns
tsu(P3D–E)
Port P3 input setup time
200
ns
tsu(P4D–E)
Port P4 input setup time
200
ns
tsu(P5D–E)
Port P5 input setup time
200
ns
tsu(P6D–E)
Port P6 input setup time
200
ns
tsu(P7D–E)
Port P7 input setup time
200
ns
tsu(P8D–E)
Port P8 input setup time
200
ns
th(E–P0D)
Port P0 input hold time
0ns
th(E–P1D)
Port P1 input hold time
0ns
th(E–P2D)
Port P2 input hold time
0ns
th(E–P3D)
Port P3 input hold time
0ns
th(E–P4D)
Port P4 input hold time
0ns
th(E–P5D)
Port P5 input hold time
0ns
th(E–P6D)
Port P6 input hold time
0ns
th(E–P7D)
Port P7 input hold time
0ns
th(E–P8D)
Port P8 input hold time
0ns
Memory expansion mode and microprocessor mode
Limits
Min.
Max.
tsu(D–E)
Data input setup time
80
ns
tsu(RDY–
φ1)
_
RDY
input setup time
80
ns
tsu(HOLD–
φ1)
_
HOLD
input setup time
80
ns
th(E–D)
Data input hold time
0ns
th(
φ1–RDY)
_
RDY
input hold time
0ns
th(
φ1–HOLD)
_
HOLD
input hold time
0ns
Unit
Symbol
Parameter
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