參數資料
型號: M37733M4LXXXHP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數: 10/34頁
文件大?。?/td> 446K
代理商: M37733M4LXXXHP
M37733M4LXXXHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
paramentic
limits
are
suject
to change.
15
Limits
Min.
Max.
tc(TB)
TBiIN input cycle time (one edge count)
250
ns
tw(TBH)
TBiIN input high-level pulse width (one edge count)
125
ns
tw(TBL)
TBiIN input low-level pulse width (one edge count)
125
ns
tc(TB)
TBiIN input cycle time (both edges count)
500
ns
tw(TBH)
TBiIN input high-level pulse width (both edges count)
250
ns
tw(TBL)
TBiIN input low-level pulse width (both edges count)
250
ns
Unit
Symbol
Parameter
Timer B input (Count input in event counter mode)
Timer B input (Pulse period measurement mode)
Limits
Min.
Max.
tc(TB)
TBiIN input cycle time (Note)
666
ns
tw(TBH)
TBiIN input high-level pulse width (Note)
333
ns
tw(TBL)
TBiIN input low-level pulse width (Note)
333
ns
Unit
Symbol
Parameter
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”.
Timer B input (Pulse width measurement mode)
Limits
Min.
Max.
tc(TB)
TBiIN input cycle time (Note)
666
ns
tw(TBH)
TBiIN input high-level pulse width (Note)
333
ns
tw(TBL)
TBiIN input low-level pulse width (Note)
333
ns
Unit
Symbol
Parameter
Note. Limits change depending on f(XIN). Refer to “DATA FORMULAS”.
A-D trigger input
Unit
Symbol
Parameter
Limits
Min.
Max.
tc(AD)
_
ADTRG
input cycle time (minimum allowable trigger)
1333
ns
tw(ADL)
_
ADTRG
input low-level pulse width
166
ns
Serial I/O
Limits
Min.
Max.
tc(CK)
CLKi input cycle time
333
ns
tw(CKH)
CLKi input high-level pulse width
166
ns
tw(CKL)
CLKi input low-level pulse width
166
ns
td(C–Q)
TXDi output delay time
100
ns
th(C–Q)
TXDi hold time
0ns
tsu(D–C)
RXDi input setup time
65
ns
th(C–D)
RXDi input hold time
75
ns
Unit
Symbol
Parameter
____
___
External interrupt INTi input, key input interrupt KIi input
Unit
Symbol
Parameter
Limits
Min.
Max.
tw(INH)
_
INTi
input high-level pulse width
250
ns
tw(INL)
_
INTi
input low-level pulse width
250
ns
tw(KIL)
_
KIi
input low-level pulse width
250
ns
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