
APPENDIX
7721 Group User’s Manual
17–5
Appendix 2. Memory assignment in SFR area
RW
Timer B2 register
4016
4116
4216
4316
4416
4516
4616
4716
4816
4916
5016
5116
5216
5316
5416
5516
5616
5716
5816
5916
5A16
5B16
5C16
5D16
5E16
5F16
4B16
4C16
4D16
4E16
4F16
4A16
Address
Timer A2 register
Timer A3 register
Timer A4 register
Timer B0 register
Timer B1 register
Processor mode register 0
One-shot start register
Timer A0 register
Up-down register
Timer A1 register
Register name
Count start register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Access characteristics
WO
(Note 1)
(Note 2)
b7
b0
RW
(Note 2)
RW
WO
State immediately after reset
0016
?
0016
b7
b0
WO
RW
(Note 1)
RW
Timer A0 mode register
Timer A4 mode register
(Note
3)
0
00
0
00
0
00
0
RW
?
Notes 1: The access characteristics at addresses 4A16 to 4F16 vary according to Timer A’s operating
mode. (Refer to “CHAPTER 8. TIMER A.”)
2: The access characteristics at addresses 5016 to 5316 vary according to Timer B’s operating
mode. (Refer to “CHAPTER 9. TIMER B.”)
3: The access characteristics for bit 5 at addresses 5B16 and 5C16 vary according to Timer B’s
operating mode. Bit 5 at address 5D16 is invalid. (Refer to “CHAPTER 9. TIMER B.”)
4: Bit 1 at address 5F16 becomes “0” immediately after reset. For the M37721S1BFP, fix this bit to
“0.”
RW
(Note
3)
RW
(Note
3)
00
0
00
?
0
00
0
?
Processor mode register 1
RW
00
0
00
0
?
0
00
0
00
0
1
?
(Note
4)
0 : “0” immediately after reset.
1 : “1” immediately after reset.
? : Undefined immediately after
reset.
: Always “0” at reading.
0
: Always undefined at reading.
: “0” immediately after reset. Fix this bit to “0.”
: It is possible to read the bit state at reading. The written value becomes valid.
: It is possible to read the bit state at reading. The written value becomes invalid.
: The written value becomes valid. It is impossible to read the bit state.
: Nothing is assigned. It is impossible to read the bit state. The written value becomes invalid.
RW
RO
WO
?
0
: Always “1” at reading.
1
Access characteristics
State immediately after reset