
7721 Group User’s Manual
13-9
DMA CONTROLLER
Fig. 13.2.3 Timing of bus request sampling
13.2 Block description
The above applies on the following conditions:
Cycle-steal transfer mode
DMA request source = external request (DMAREQi)
1-bus cycle transfer
No Wait
E
HOLD
BUS REQUEST (Hold)
Bus request sampling
ST1, ST0
When access
is complete in
1 bus cycle
When 16-bit data is accessed
in a unit of 8 bits
Transition of right
to use bus
(1, 1)
(0, 0)
(1, 1)
Refresh
E
Refresh request
BUS REQUEST(DRAMC)
Bus request sampling
ST1, ST0
(0, 0)
Bus used by
CPU
s DRAM refresh
This is the term in which the bus is not
used so that sampi ng is performed every
1 cycle of
.
Sampling is performed after completion of
a refresh cycle.
1 bus cycle.
H
Hold state
H
DMA transfer
H
s Hold
s DMA transfer
Refresh
(1, 1)
Hold state
E
DMAREQi
DMAi request bit
BUS REQUEST (DMAC)
Bus request sampling
ST1, ST0
(1, 1)
(0, 1)
(1, 1)
(0, 1)
(1, 1)
(1, 0)
(1, 1)
(1, 0)
DMA transfer
This is the term in which the bus is not
used so that sampling is performed every
1 cycle of
.
This is at Holol state so that sampling is
performed every 1 cycle of
.
Sampling is performed after completion of
1 bus cycle.
This is the term in which the bus is not
used so that sampling is performed every
1 cycle of
Sampling is performed after completion of
Sampling is performed after complet on of
1-unit transfer.
1 bus cycle.
s CPU
E
Bus request sampling
ST1, ST0
(1, 1)
Bus used by
CPU
by CPU
Bus used by CPU
Transition of right
to use bus
Transition of right
to use bus
Transition of right
to use bus
Transition of right
to use bus
Transition of right
to use bus
Transition of right
to use bus
Transition of right
to use bus
Transition of right
to use bus
Transition of right
to use bus
Transition of right
to use bus
Transition of right
to use bus
.
This is the term in which the bus is not
used so that sampling is performed every
1 cycle of
Sampling is performed after completion of
1 bus cycle.
16-bit data is accessed in a unit of 8 bits,
so that sampling is performed after
completion of the second bus cycle.
Bus used
.
i