參數(shù)資料
型號(hào)： M37702M2BXXXFP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機(jī)
文件頁(yè)數(shù)： 9/59頁(yè)
文件大?。?/td> 811K
代理商： M37702M2BXXXFP
9
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
5. Index register length flag (x)
The index register length flag determines whether index register X
and index register Y are used as 16-bit registers or as 8-bit regis-
ters. The registers are used as 16-bit registers when flag x is “0”
and as 8-bit registers when it is “1”. This flag can be set and reset
with the SEP and CLP instructions.
6. Data length flag (m)
The data length flag determines whether the data length is 16-bit
or 8-bit. The data length is 16-bit when flag m is “0” and 8-bit when
it is “1”. This flag can be set and reset with the SEM and CLM in-
structions or with the SEP and CLP instructions.
7. Overflow flag (V)
The overflow flag has meaning when addition or subtraction is
performed a word as signed binary number. When the data length
flag m is “0”, the overflow flag is set when the result of addition or
subtraction is outside the range between –32768 and +32767.
When the data length flag m is “1”, the overflow flag is set when
the result of addition or subtraction is outside the range between
–128 and +127. It is reset in all other cases. The overflow flag can
also be set and reset directly with the SEP, and CLV or CLP in-
structions.
8. Negative flag (N)
The negative flag is set when the result of arithmetic operation or
data transfer is negative (If data length flag m is “0”, when data bit
15 is “1”. If data length flag m is “1”, when data bit 7 is “1”.) It is re-
set in all other cases. It can also be set and reset with the SEP
and CLP instructions.
9. Processor interrupt priority level (IPL)
The processor interrupt priority level (IPL) consists of 3 bits and
determines the priority of processor interrupts from level 0 to level
7. Interrupt is enabled when the interrupt priority of the device re-
questing interrupt (set using the interrupt control register) is higher
than the processor interrupt priority. When interrupt is enabled, the
current processor interrupt priority level is saved in a stack and the
processor interrupt priority level is replaced by the interrupt prior-
ity level of the device requesting the interrupt. Refer to the section
on interrupts for more details.
BUS INTERFACE UNIT
The CPU operates on an internal clock frequency which is ob-
tained by dividing the external clock frequency f(X
IN
) by two. This
frequency is twice the bus cycle frequency. In order to speed-up
processing, a bus interface unit is used to pre-fetch instructions
when the data bus is idle. The bus interface unit synchronizes the
CPU and the bus and pre-fetches instructions. Figure 4 shows the
relationship between the CPU and the bus interface unit. The bus
interface unit has a program address register, a 3-byte instruction
queue buffer, a data address register, and a 2-byte data buffer.
The bus interface unit obtains an instruction code from memory
and stores it in the instruction queue buffer, obtains data from
memory and stores it in the data buffer, or writes the data from the
data buffer to the memory.
Fig. 4 Relationship between the CPU and the bus interface unit
CPU
Bus interface
unit
E
ALE
BYTE
HOLD
BHE
R/
W
D
15
to D
8
A
23
to A
0
D
7
to D
0
D'
15
to
D'
8
Control signal
D'
7
to D'
0
A'
23
to A'
0
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