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參數(shù)資料
| 型號： | M37641F8FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 46/149頁 |
| 文件大?。?/td> | 1997K |
| 代理商： | M37641F8FP |
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46
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
USB Interrupts
The USB FCU has two interrupts, USB Function Interrupt and
USB SOF (Start Of Frame) Interrupt.
G
USB Function Interrupt (USBF-INT)
The USBF-INT is usable for the USB data flow control and power
management. The USBF-INT request occurs at data transmit/re-
ceive completion, overrun/underrun, reset, or receiving suspend/
resume signal. To enable this interrupt, the USB function interrupt
enable bit in the interrupt control register A (address 0005
16
) and
the respective bit in the USB interrupt enable registers 1 and 2
(addresses 00054
16
and 00055
16
) must be set to
“
1
”
. When set-
ting bit 7 in USB interrupt enable register 2 to
“
1
”
, the suspend
interrupt and the resume interrupt are enabled.
Endpoint x (x = 0 to 4) IN interrupt request occurs when the USB
Endpoint x IN interrupt status flag (INTST 0, 2, 4, 6, 8) of USB in-
terrupt status registers 1 and 2 (addresses 0052
16
and 0053
16
) is
“
1
”
. The USB Endpoint x IN interrupt status flag is set to
“
1
”
when
the respective endpoint IN_PKT_RDY bit is
“
1
”
.
Endpoint x (x = 0 to 4) OUT interrupt request occurs when the
USB endpoint x OUT interrupt status flag (INTST3, 5, 7, 9) in USB
interrupt status registers 1 and 2 is set to
“
1
”
. The USB Endpoint x
OUT interrupt status flag is set to
“
1
”
when the respective endpoint
OUT_PKT_RDY flag is
“
1
”
.
The overrun/underrun interrupt request occurs when the USB
overrun/underrun interrupt status flag (INTST12) in USB interrupt
status register 2 is set to
“
1
”
. This flag is set to
“
1
”
when the FIFO
data overruns or underruns in isochronous transfer mode.
The USB reset interrupt request occurs when the USB reset inter-
rupt status flag (INTST13) in USB interrupt status register 2 is set
to
“
1
”
. This flag is set when the SE0 is detected on the D+/D- line
for at least 2.5
μ
s. When this situation happens, all USB internal
registers (addresses 0050
16
to 005E
16
), except this flag, are ini-
tialized to the default state at reset. The USB reset interrupt is
always enabled.
The suspend/resume interrupt request occurs when either the
USB resume signal interrupt status flag (INTST14) or the USB
suspend signal interrupt status flag (INTST15) in USB interrupt
status register 2 is set to
“
1
”
.
The bits in both interrupt status registers 1 and 2 can be cleared
by writing
“
1
”
to each bit.
G
USB SOF interrupt
The USB SOF interrupt is usable in isochronous transfers. This in-
terrupt request occurs when an SOF packet is received. To enable
a USB SOF interrupt, set the USB SOF interrupt enable bit of in-
terrupt control register A to
“
1
”
.
Suspend/Resume Functions
If no bus activity is detected on the D+/D- line for at least 3 ms, the
USB suspend signal detect flag (SUSPEND) of the USB power
control register (address 0051
16
) and the USB suspend signal in-
terrupt status flag of USB interrupt status register 2 are set to
“
1
”
and the suspend interrupt request occurs. The following procedure
must be executed after pushing the internal registers (A, X, Y ) to
memories during the suspend interrupt process routine.
(1) Clear all bits of USB interrupt status register 1 (address
0052
16
) and USB interrupt status register 2 (address 0053
16
)
to
“
0
”
.
(2) Set the USB clock enable bit to
“
0
”
. (After disabling the USB
clock, do not write to any of the USB internal registers (ad-
dresses 0050
16
to 0064
16
), except for the USB control register
(address 0013
16
), clock control register (address 001F
16
), and
frequency synthesizer control register (address 006C
16
).
(3) Set the frequency synthesizer enable bit to
“
0
”
.
(4) Set the USB line driver current control bit to
“
1
”
. (Always keep
the USB line driver current control bit set to
“
0
”
during USB
function operations. When operating at Vcc = 3.3 V, this bit
does not need to be set.)
(5) Keep total drive current at 500
μ
A or less.
(6) Disable the timer 1 interrupt.
(7) Disable the timer 2 interrupt. (Disable all the other external in-
terrupts.)
(8) Set the timer 1 interrupt request bit to
“
0
”
.
(9) Set the timer 2 interrupt request bit to
“
0
”
.
(10) Set the interrupt disable flag (I) to
“
0
”
.
(11) Execute the STP instruction.
At this point, the MCU will be in stop mode (suspend mode). Be-
fore executing the STP instruction, make sure to set the USB
function interrupt request bit (bit 0 at address 0002
16
) to
“
0
”
and
the USB function interrupt enable bit (bit 0 at address 0005
16
) to
“
1
”
.
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