參數(shù)資料
型號(hào): M37641F8FP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù): 27/149頁(yè)
文件大小: 1997K
代理商: M37641F8FP
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27
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
Timer 1, Timer 2, Timer 3
Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for
each timer can be selected by timer 123 mode register.
G
Timers 1, 2 Write Control
When the Timers 1, 2 Write Control Bit is
1
and the values are
written in the address of timers 1 and 2, the values are loaded only
in their latches. The values in the latches are loaded in timers 1
and 2 after timers 1 and 2 underflow.
When the Timers 1, 2 Write Control Bit is
0
and the values are
written in the address of timers 1 and 2, the values are loaded in
the timers 1 and 2 and their latches at the same time.
G
Timers 1, 2 Output Control
A signal of which polarity is inverted each time the timer selected
by the T
OUT
Factor Select Bit underflows is output from the T
OUT
pin. This is enabled by setting the T
OUT
Output Control Bit to
1
.
When the T
OUT
Output Active Edge Switch Bit is
0
, the T
OUT
pin
starts pulses output beginning at
H
; when this bit is
1
, the T
OUT
pin starts pulses output beginning at
L
.
When using a timer in this mode, set the port P5
1
direction regis-
ter to output mode.
I
Notes
G
Timer 1 to Timer 3
Switching of the count sources of timers 1 to 3 does not affect the
values of reload latches. However, that may make count operation
started. Therefore, write values again in the order of timers 1, 2
and then timer 3 after their count sources have been switched.
G
Timers 1, 2 Write Control
When the value is to be written in latch only, unexpected value
may be set in the timer if the writing in the latch and the timer un-
derflow are performed at the same timing.
Fig. 22 Structure of timer 123 mode register
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