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參數(shù)資料
| 型號： | M37640E8FS |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 74/96頁 |
| 文件大?。?/td> | 1477K |
| 代理商： | M37640E8FS |
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74
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1.24.1 Frequency Synthesizer Circuit
The Frequency Synthesizer Circuit generates a 48MHz
clock needed by the USB block and a clock f
SYN
that
are both a multiple of the external input reference
clock f
IN
. A block diagram of the circuit is shown in
Figure 1.91.
The frequency synthesizer consists of a prescaler, fre-
quency multiplier macro, a frequency divider macro,
and four registers, namely FSM1, FSM2, FSC and
FSD. Two multiply registers (FSM1, FSM2) control the
frequency multiply amount. Clock f
IN
is prescaled us-
ing FSM2 to generate f
PIN
. f
PIN
is multiplied using
FSM1 to generate an f
VCO
clock which is then divided
using FSD to produce the clock f
SYN
. The f
VCO
clock
is optimized for 48 MHz operation and is buffered and
sent out of the frequency synthesizer block as signal
f
USB
. This signal is used by the USB block. The clock
block diagram is shown in Figure 1.92.
Clock f
PIN
is a divided down version of clock f
IN
, which
can be either f(X
in
) or f(XC
in
). The default clock after re-
set is fXin. The relationship between f
PIN
and the clock
input to the prescaler (f
IN
) is as follows:
f
PIN
= f
IN
/2(n+1) where n is a decimal number between
0 and 254. (See Figure 1.95).
Setting FSM2 to 255 disables the prescaler and f
PIN
=
f
IN
.
Data Bus
FSM2
FSM1
FSC
FSD
006E
006D
006C
006F
Frequency
Multiplier
Frequency
Divider
8
LS
Bit
f
IN
f
VCO
f
SYN
f
USB
Prescaler
8
f
PIN
The relationship between f
PIN
, f
VCO
, f
SYN
, and f
USB
is
as follows:
f
VCO
= f
PIN
x 2(n+1) where n is the decimal equivalent
of the value loaded in FSM1. (See Figure 1.94).
n must be chosen such that f
VCO
equals 48 MHz.
f
SYN
= f
VCO
/ 2(m+1) where m is the decimal equiva-
lent of the value loaded in FSD. (See Figure 1.96).
Setting m=255 disables the divider and disables f
SYN
.
f
USB
is a buffered version of f
VCO
, i.e., FSD has no ef-
fect on f
USB
.
Setting USB control register bit 5 to “0” disables f
USB
by tri-stating the buffer.
The FSC0 bit in the FSC Register (FSC) enables the
frequency synthesizer block. When disabled (FSC0 =
“0”), f
VCO
is held at either a high or low state. When
the frequency synthesizer control bit is active (FSC0
= “1”), a lock status (LS = “1”) indicates that f
SYN
and
fVCO are the correct frequency. The LS and FSCO
control bits in the FSC register are shown in Figure
1.93.
When using the frequency synthesizer, a low-pass fil-
ter must be connected to the LPF pin.
Once the frequency synthesizer is enabled, a delay of
2-5ms is recommended before the output of the fre-
quency synthesizer is used. This is done to allow the
output to stabilize. It is also recommended that none
of the registers be modified once the frequency syn-
thesizer is enabled as it will cause the output to be
temporarily (2-5ms) unstable.
Fig. 1.91. Frequency Synthesizer Circuit
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