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參數(shù)資料
| 型號： | M37640E8FS |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 59/96頁 |
| 文件大?。?/td> | 1477K |
| 代理商： | M37640E8FS |
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59
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The
USB Endpoint 0 IN CSR
Control & Status
Register
, shown in Figure 1.62, contains the control
and status information of Endpoint 0.
IN0CSR0 (OUT_PKT_RDY):
The USB FCU sets this
bit to a “1” upon receiving a valid SETUP/OUT token
from the host. The CPU clears this bit after unloading
the FIFO, by way of writing a “1” to IN0CSR6. The
CPU should not clear the OUT_PKT_RDY bit before it
finishes decoding the host request. If IN0CSR2
(SEND_STALL) needs to be set (because the CPU
decodes an invalid or unsupported request), the set-
ting of IN0CSR6 = “1” and IN0CSR2 = “1” should be
done in the same CPU write.
IN0CSR1 (IN_PKT_RDY):
The CPU writes a “1” to
this bit after it finishes writing a packet of data to the
endpoint 0 FIFO. The USB FCU clears this bit after
the packet has been successfully transmitted to the
host, or the IN0CSR5 (SETUP_END) bit is set.
IN0CSR2 (SEND_STALL):
The CPU writes a “1” to
this bit if it decodes an invalid or unsupported request
from the host. If the OUT_PKT_RDY bit is a “1” at the
time the CPU wants to set the SEND_STALL bit is to
a
“1”,
the
CPU
SERVICED_OUT_PKT_RDY to a “1” to clear the
OUT_PKT_RDY. The USB FCU returns a STALL hand-
shake for all subsequent IN/OUT transactions (during
control transfer data or status stages) while this bit is
set. The CPU writes a “0” to this bit to clear it.
must
also
set
IN0CSR3 (DATA_END):
For control transfers, the CPU
writes a “1” to this bit after it writes (IN data phase) or
reads (OUT data phase) the last packet of data from/
to the FIFO. This bit indicates to the USB FCU that
the specific amount of data in the setup phase has
been transferred. The USB FCU will advance to the
status phase once this bit is set. When the status
phase completes, the USB FCU clears this bit. When
this bit is set to a “1” and the host again requests or
sends more data to the device, the USB FCU returns
a STALL handshake and terminates the current control
transfer.
IN0CSR4 (FORCE_STALL):
The USB FCU sets this bit
to a “1” to report an error status if the one of the follow-
ing occurs:
Host sends an IN or OUT token in the absence of a
SETUP stage
Host sends a bad data toggle in the STATUS stage,
i.e. DATA0 is used
Host sends a bad data toggle in the SETUP stage,
i.e. DATA1 is used
Host requests more data than specified in the
SETUP stage, i.e. IN token comes after DATA_END
bit is set
Host sends more data than specified in the SETUP
stage, i.e. OUT token comes after DATA_END bit is
set
Host sends larger data packet than MAXP size of the
corresponding endpoint.
INOCSR7
INOCSR5
INOCSR4 INOCSR3
INOCSR2
INOCSR1
INOCSR0
MSB
7
LSB
0
INOCSR6
Address: 0059
16
Access: R/W
Reset: 00
16
INOCSR0
OUT_PKT_RDY Flag (bit 0) (Read Only - Write "0")
0: Out packet is not ready
1: Out packet is ready
IN_PKT_RDY Bit (bit 1)(Write "1" only or Read)
0: In packet is not ready
1: In packet is ready
SEND_STALL Bit (bit 2)(Write "1" only or Read)
0: No action
1: Stall Endpoint 0 by the CPU
DATA_END Bit (bit 3)(Write "1" only or Read)
0: No action
1: Last packet of data transfered from/to the FIFO
Force_STALL Flag (bit 4)(Write "0" only or Read)
0: No action
1: Stall Endpoint 0 by the USB FCU
SETUP_END Flag (bit 5) (Read Only - Write "0")
0: No Action
1: Control transfer ended before the specific length of data is transferred during
the data phase
SERVICED_OUT_PKT_RDY Bit (bit 6) (Write Only - Read "0")
0: No change
1: Clear the OUT_PKT_RDY bit (INOCSR0)
SERVICED_SETUP_END Bit (bit 7)(Write Only - Read "0")
0: No change
1: Clear the SETUP_END bit (INOCSR5)
INOCSR1
INOCSR2
INOCSR3
INOCSR4
INOCSR5
INOCSR6
INOCSR7
Fig. 1.62. USB Endpoint 0 IN CSR (IN_CSR)
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