參數(shù)資料
型號(hào)： M37640E8FP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 87/96頁(yè)
文件大?。?/td> 1477K
代理商： M37640E8FP
87
Ver 1.4
MITSUBISHI MICROCOMPUTERS
7640 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2.5. Memory Expansion Mode and Microprocessor Mode Timing
(Vcc = 4.15 to 5.25V, Vss = 0V, Ta = -20 to 85°C unless otherwise noted)
Note : Measurement conditions: Iohl =
±
5ma, C
L
= 50pF
Symbol
Parameter
Limits
Typ.
Unit
Min.
Max.
tc(
Φ
)
twh(
Φ
)
twl(
Φ
)
td(
Φ
-AH)
tv(
Φ
-AH)
td(
Φ
-AL)
tv(
Φ
-AL)
td(
Φ
-WR)
tv(
Φ
-WR)
td(
Φ
-RD)
tv(
Φ
-RD)
td(
Φ
-SYNC)
Φ
clock cycle time
83.33
ns
Φ
clock
“
H
”
pulse width
0.5*tc(
Φ
)-5
0.5*tc(
Φ
)-5
ns
Φ
clock
“
L
”
pulse width
Address bus AB15-AB8 delay time with respect to
Φ
Address bus AB15-AB8 valid time with respect to
Φ
Address bus AB7-AB0 delay time with respect to
Φ
Address bus AB7-AB0 valid time with respect to
Φ
ns
31
ns
5
ns
33
ns
5
ns
WR delay time
6
ns
WR valid time
3
ns
RD delay time
6
ns
RD valid time
3
ns
SYNC
OUT
delay time
6
ns
tv(
Φ
-SYNC)
SYNC
OUT
valid time
4
ns
td(
Φ
-DMA)
DMA
OUT
delay time
25
ns
tv(
Φ
-DMA)
tsu(RDY-
Φ
)
th(
Φ
-RDY)
tsu(HOLD-
Φ
)
th(
Φ
-HOLD)
td(
Φ
-HLDAL)
tv(
Φ
-HLDAH)
tsu(DB-
Φ
)
th(
Φ
-DB)
td(
Φ
-DB)
DMA
OUT
valid time
RDY setup time with respect to
Φ
RDY hold time with respect to
Φ
5
ns
21
ns
0
ns
HOLD setup time
21
ns
HOLD hold time
0
ns
HLDAL delay time
HLDAH delay time
Data bus setup time with respect to
Φ
Data bus hold time with respect to
Φ
Data bus delay time with respect to
Φ
25
ns
25
ns
7
ns
0
ns
22
ns
tv(
Φ
-DB)
Data bus valid time with respect to
Φ
(Note)
13
ns
twl(WR)
WR pulse width
RD pulse width
0.5*tc(
Φ
)-5
0.5*tc(
Φ
)-5
0.5*tc(
Φ
)-28
0.5*tc(
Φ
)-30
ns
twl(RD)
ns
td(AH-WR)
WR delay time after stable address AB15-AB8
ns
td(AL-WR)
WR delay time after stable address AB7-AB0
Address bus AB15-AB8 valid time with respect to WR
ns
tv(WR-AH)
0
ns
tv(WR-AL)
Address bus AB7-AB0 valid time with respect to WR
0
ns
td(AH-RD)
RD delay time after stable address AB15-AB8
0.5*tc(
Φ
)-28
0.5*tc(
Φ
)-30
ns
td(AL-RD)
RD delay time after stable address AB7-AB0
ns
tv(RD-AH)
Address bus AB15-AB8 valid time with respect to RD
Address bus AB7-AB0 valid time with respect to RD
0
ns
tv(RD-AL)
0
ns
tsu(RDY-WR)
RDY setup time with respect to WR
27
ns
th(WR-RDY)
RDY hold time with respect to WR
0
ns
tsu(RDY-RD)
RDY setup time with respect to RD
27
ns
th(RD-RDY)
RDY hold time with respect to RD
0
ns
tsu(DB-RD)
Data bus setup time with respect to RD
13
ns
th(RD-DB)
Data bus hold time with respect to RD
0
ns
td(WR-DB)
Data bus delay time with respect to WR
20
ns
tv(WR-DB)
Data bus valid time with respect to WR
Note
10
ns
tr(D+), tr(D-)
USB output rise time, CL=50 pF
4
20
ns
tf (D+), tf(D-)
USB output fall time, CL=50 pF
4
20
ns
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