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參數(shù)資料
| 型號： | M37560ME-XXXGP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 36/65頁 |
| 文件大小： | 955K |
| 代理商： | M37560ME-XXXGP |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
36
A-D CONVERTER
The functional blocks of the A-D converter are described below.
[A-D Conversion Register (AD)] 0035
16
The A-D conversion register is a read-only register that contains
the result of an A-D conversion. When reading this register during
an A-D conversion, the previous conversion result is read.
[A-D Control Register (ADCON)] 0034
16
The A-D control register controls the A-D conversion process. Bits
0 to 2 of this register select specific analog input pins. Bit 3 signals
the completion of an A-D conversion. The value of this bit remains
at
“
0
”
during an A-D conversion, then changes to
“
1
”
when the A-
D conversion is completed. Writing
“
0
”
to this bit starts the A-D
conversion. Bit 4 controls the transistor which breaks the through
current of the resistor ladder. When bit 5, which is the AD external
trigger valid bit, is set to
“
1
”
, this bit enables A-D conversion even
by a falling edge of an ADT input. Set ports which share with ADT
pins to input when using an A-D external trigger.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AV
SS
and V
REF
by 256, and outputs the divided voltages.
Channel Selector
The channel selector selects one of the input ports P6
7
/AN
7
–
P6
0
/
AN
0
.
Comparator and Control Circuit
The comparator and control circuit compare an analog input volt-
age with the comparison voltage and store the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
interrupt request bit to
“
1
”
.
Note that the comparator is constructed linked to a capacitor, so
set f(X
IN
) to at least 500kHz during A-D conversion.
Use the clock divided from the main clock X
IN
as the internal clock
φ
.
Fig. 36 A-D converter block diagram
Fig. 35 Structure of A-D control register
A
(
A
-
D
D
C
n
0
0
0
0
1
1
1
1
c
o
O
n
N
t
r
o
:
l
a
r
d
e
g
r
i
e
s
t
e
s
r
d
s
0
0
3
4
1
6
)
A
V
REF
input switch bit
0 : OFF
1 : ON
A
e
x
t
e
r
n
a
0
:
A
-
D
e
1
:
A
-
D
e
In
e
r
r
u
p
t
s
o
0
:
I
n
t
e
r
r
c
o
n
v
1
:
I
n
t
e
r
r
i
n
p
u
t
N
t
u
s
e
d
(
D
c
o
:
:
n
C
C
v
o
o
e
n
n
r
v
v
s
e
e
i
o
r
r
n
s
s
o
o
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i
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c
p
p
o
l
e
r
p
t
i
g
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o
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r
e
t
e
b
s
d
i
t
0
1
i
i
o
s
m
A
a
0
0
1
1
0
0
1
1
l
o
g
0
1
0
1
0
1
0
1
i
:
:
:
:
:
:
:
:
n
p
u
6
0
/
6
1
/
6
2
/
6
3
/
6
4
/
6
5
/
6
6
/
6
7
/
t
p
A
A
A
A
A
A
A
A
i
N
0
N
1
N
2
N
3
N
4
N
5
N
6
N
7
n
s
e
l
e
c
t
i
o
n
b
i
t
s
P
P
P
P
P
P
P
P
D
l
x
x
u
u
e
u
f
r
e
t
t
t
r
p
r
s
p
a
t
r
e
e
c
t
i
t
l
l
u
i
g
r
r
e
r
o
r
i
n
r
g
n
n
e
n
e
g
n
e
a
a
s
q
c
q
r
t
t
l
v
r
r
e
e
m
e
a
i
g
i
g
c
s
l
g
g
t
i
t
p
t
i
d
e
e
o
a
l
e
a
b
r
r
n
t
t
t
i
i
v
b
A
e
A
t
n
l
l
e
u
o
u
v
a
l
i
t
D
l
i
d
a
i
-
d
D
d
b
7
b
0
t
s
T
o
s
“
0
”
w
h
e
n
r
e
a
d
)
C
o
m
p
a
r
a
t
o
r
A-D control circuit
ADT/A-D interrupt request
A
V
S
S
V
REF
P
6
0
/
6
1
/
S
I
N
2
/
A
A
N
0
N
1
D
a
t
a
b
u
s
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
b
7
b
0
A-D conversion
register
8
Resistor ladder
C
h
a
n
e
l
s
e
l
e
c
t
o
r
P
6
7
/
A
N
7
P
6
6
/
A
N
6
P
6
5
/
A
N
5
P
6
4
/
A
N
4
P6
3
/S
CLK22
/AN
3
P6
2
/S
CLK21
/AN
2
P
S
O
U
T2
/
P
5
7
/
A
D
T
/
D
A
2
3
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