參數(shù)資料
型號(hào)： M37560ME-XXXGP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 34/65頁(yè)
文件大小： 955K
代理商： M37560ME-XXXGP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7560 Group
34
PULSE WIDTH MODULATION (PWM)
The 7560 group has a PWM function with an 8-bit resolution,
based on a signal that is the clock input X
IN
or that clock input di-
vided by 2.
Data Setting
The PWM output pin also functions as ports P5
0
and P5
1
. Set the
PWM period by the PWM prescaler, and set the period during
which the output pulse is an
“
H
”
by the PWM register.
If PWM count source is f(X
IN
) and the value in the PWM prescaler
is n and the value in the PWM register is m (where n = 0 to 255
and m = 0 to 255) :
PWM period = 255
(n+1)/f(X
IN
)
= 31.875
(n+1)
μ
s (when f(X
IN
) = 8 MHz)
Output pulse
“
H
”
period = PWM period
m/255
= 0.125
(n+1)
m
μ
s
(when f(X
IN
) = 8 MHz)
PWM Operation
When at least either bit 1 (PWM
0
function enable bit) or bit 2
(PWM
1
function enable bit) of the PWM control register is set to
“
1
”
, operation starts by initializing the PWM output circuit, and
pulses are output starting at an
“
H
”
. When one PWM output is en-
abled and that the other PWM output is enabled, PWM output
which is enabled to output later starts pulse output from halfway.
When the PWM register or PWM prescaler is updated during
PWM output, the pulses will change in the cycle after the one in
which the change was made.
Fig. 31 Timing of PWM cycle
Fig. 32 Block diagram of PWM function
31.875
m
(n+1)
255
μ
s
T = [31.875
(n+1)]
μ
s
PWM output
m: Contents of PWM register
n : Contents of PWM prescaler
T : PWM cycle (when f(X
IN
) = 8 MHz)
Data bus
C
s
”
o
e
u
l
e
n
c
t
t
i
s
o
o
n
u
b
r
c
i
t
e
“
0
“
1
”
P
a
W
e
r
M
p
e
p
r
e
s
c
l
r
-
l
a
t
c
h
PWM
register pre-latch
P
c
W
a
M
e
l
p
r
e
s
l
r
a
t
c
h
P
i
s
W
t
e
M
r
a
r
e
g
l
t
c
h
Transfer control circuit
PWM circuit
1
/
2
X
IN
PWM
0
function
enable bit
P
o
r
t
P
5
1
P
W
M
p
r
e
s
c
a
l
e
r
PWM
1
function
enable bit
Port P5
0
P
l
a
o
r
t
t
h
P
5
1
c
Port P5
0
lacth
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