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參數(shù)資料
| 型號(hào)： | M37560M8A-XXXGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 5 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 31/73頁 |
| 文件大?。?/td> | 888K |
| 代理商： | M37560M8A-XXXGP |
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Rev.1.02
Jul 31, 2003
page 35 of 69
7560 Group (A version)
Fig. 33 Timing of serial I/O2 function
D7
D0
D1
D2
D3
D4
D5
D6
Synchronous clock
(Note 1)
Serial I/O2 output SOUT2
Serial I/O2 input SIN2
Serial I/O2 register
write signal
(Notes 2, 3)
Serial I/O2 interrupt request bit = “1”
1: When the internal clock is selected as the synchronous clock, the divide ratio can be selected by setting bits 0 to 2 of the
serial I/O2 control register.
2: When the internal clock is selected as the synchronous clock, the SOUT2 pin goes to high impedance after transfer
completion.
3: When the external clock is selected as the synchronous clock, the SOUT2 pin keeps D7 output level after transfer
completion. However, if synchronous clocks input are carried on, the transmit data will be output continuously from the
SOUT2 pin because shifts of serial I/O2 shift register is continued as long as synchronous clocks are input.
Notes
●Serial I/O2 Operating
The serial I/O2 counter is initialized to “7” by writing to the serial
I/O2 register.
After writing, whenever a synchronous clock changes from “H” to
“L”, data is output from the SOUT2 pin. Moreover, whenever a syn-
chronous clock changes from “L” to “H”, data is taken in from the
SIN2 pin, and 1 bit shift of the serial I/O2 register is carried out si-
multaneously.
When the internal clock is selected as a synchronous clock, it is
as follows if a synchronous clock is counted 8 times.
Serial I/O2 counter = “0”
Synchronous clock stops in “H” state
Serial I/O2 interrupt request bit = “1”
The SOUT2 pin is in a high impedance state after transfer is com-
pleted.
When the external clock is selected as a synchronous clock, if a
synchronous clock is counted 8 times, the serial I/O2 interrupt re-
quest bit is set to “1”, and the SOUT2 pin holds the output level of
D7. However, if a synchronous clock continues being input, the
shift of the serial I/O2 register is continued and transmission data
continues being output from the SOUT2 pin.
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