參數(shù)資料
型號： M37549G2-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24
封裝： 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24
文件頁數(shù)： 8/86頁
文件大?。?/td> 1375K
代理商： M37549G2-XXXFP
Rev.2.02
Mar 31, 2009
Page 14 of 81
REJ03B0202-0202
7549 Group
Fig 10. Structure of Function set ROM data 0
Fig 11. Structure of Function set ROM data 1
Fig 12. Structure of Function set ROM data 2
Low voltage detection circuit valid bit
0: Low voltage detection circuit invalid
1: Low voltage detection circuit valid
Set “0” to this bit certainly.
Set “1” to this bit certainly.
b7
Function set ROM data 0
(FSROM0: address FFD816)
b0
Oscillation method selection bits (Note 1)
b1 b0
0 0: Clock pins not used (P20/XOUT and P21/XIN are used as
I/O ports)
0 1: Ceramic resonator or quarts-crystal oscillator
1 0: 32 kHz quarts-crystal oscillator
1 1: External clock input (P21/XIN pin is used as I/O port)
Low voltage detection circuit valid bit in the stop mode (Note 2)
0: Low voltage detection circuit invalid in the stop mode
1: Low voltage detection circuit valid in the stop mode
Set “0” to these bits certainly.
Set “1” to this bit certainly.
b7
Function set ROM data 1
(FSROM1: address FFD916)
b0
Notes 1: The P20/XOUT and P21/XIN pins build in an on-chip oscillator. Even if these pins are used
as I/O ports, the oscillator circuit is enabled when the MCU’s Vcc voltage drops below
the operation limit voltage. In this case these pins may output undefined values.
2: When the Low voltage detection circuit is set to be valid in the stop mode, the dissipation
current in the stop mode is increased.
Watchdog timer source clock selection bit
0 : Low-speed on-chip oscillator/16
1 :
φSOURCE/16
Watchdog timer disable bit
0 : Watchdog timer enabled
1 : Watchdog timer disabled
Watchdog timer H count source initial value
selection bit
0 : Initial value of bit 7 of WDTCON
after reset release is “0”
1 : Initial value of bit 7 of WDTCON
after reset release is “1”
STP instruction function selection bit
0 : System enters into the stop mode
at the STP instruction execution
1 : Internal reset occurs at the STP
instruction execution
Low-speed on-chip oscillator control bit
(Note 1)
0 : Stop of low-speed on-chip oscillator
disabled
1 : Stop of low-speed on-chip oscillator
enabled
Set “0” to these bits certainly.
b7
Function set ROM data 2
(FSROM2: address FFDA16)
b0
Note 1: If “0” is set to this bit, it is not possible to write “1” to bit 0 in the clock
mode register. Also, the low-speed on-chip oscillator does not stop
even if in the stop mode.
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