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參數(shù)資料
| 型號(hào)： | M37549G2-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24 |
| 封裝： | 5.30 X 10.10 MM, 0.80 MM PITCH, PLASTIC, SSOP-24 |
| 文件頁數(shù)： | 77/86頁 |
| 文件大?。?/td> | 1375K |
| 代理商： | M37549G2-XXXFP |
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Rev.2.02
Mar 31, 2009
Page 77 of 81
REJ03B0202-0202
7549 Group
Notes on Interrupts
1. Change of relevant register settings
1. Change of relevant register settings
When not requiring for the interrupt occurrence synchronous
with the following case, take the sequence shown in Figure 5.
When switching external interrupt active edge
When switching interrupt sources of an interrupt vector
address where two or more interrupt sources are allocated
Fig 89. Sequence of changing relevant register
<Reason>
When setting the followings, the interrupt request bit of the
corresponding interrupt may be set to “1”.
When switching external interrupt active edge
INT0 interrupt edge selection bit
(bit 0 of Interrupt edge selection register (address 003A16))
INT1 interrupt edge selection bit
(bit 1 of Interrupt edge selection register)
Capture 0 interrupt edge selection bit
(bits 1 and 0 of capture mode register (address 3216))
Capture 1 interrupt edge selection bit
(bits 3 and 2 of capture mode register)
2. Check of interrupt request bit
When executing the BBC or BBS instruction to determine an
interrupt request bit immediately after this bit is set to “0”, take
the following sequence.
<Reason>
If the BBC or BBS instruction is executed immediately after an
interrupt request bit is cleared to “0”, the value of the interrupt
request bit before being cleared to “0” is read.
Fig 90. Sequence of check of interrupt request bit
Notes on Timers
1. Division Ratio of Timers 1, 2, and A
When n (0 to 255) is written to a timer latch, the frequency
division ratio is 1/(n
+1).
2. Switching Count Source of Timers 1, 2, and A
When a count source of timer 1, timer 2 or timer A is switched,
stop a count of the timer.
3. Reading from and Writing to Timers 1, 2, and
Prescaler 12
or
or
Set the interrupt edge selection bit active edge
switch bit, or the interrupt source selection bit.
NOP (One or more instructions)
Set the corresponding interrupt enable bit to
“0” (disabled).
Set the corresponding interrupt request bit to “0”
(no interrupt request).
Set the corresponding interrupt enable bit to “1”
(enabled).
NOP (one or more instructions)
Set the interrupt request bit to “0” (no interrupt issued)
Execute the BBC or BBS instruction
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