REJ03B0160-0122 Rev.1.22 Mar 13, 2009
page 23 of 100
7546 Group
Fig. 20 Interrupt control
Interrupt Disable Flag
The interrupt disable flag is assigned to bit 2 of the processor sta-
tus register. This flag controls the acceptance of all interrupt
requests except for the BRK instruction. When this flag is set to
“1”, the acceptance of interrupt requests is disabled. When it is set
to “0”, the acceptance of interrupt requests is enabled. This flag is
set to “1” with the SEI instruction and set to “0” with the CLI in-
struction.
When an interrupt request is accepted, the contents of the proces-
sor status register are pushed onto the stack while the interrupt
disable flag remains set to “0”. Subsequently, this flag is automati-
cally set to “1” and multiple interrupts are disabled.
To use multiple interrupts, set this flag to “0” with the CLI instruc-
tion within the interrupt processing routine.
The contents of the processor status register are popped off the
stack with the RTI instruction.
Interrupt Request Bits
Once an interrupt request is generated, the corresponding inter-
rupt request bit is set to “1” and remains “1” until the request is
accepted. When the request is accepted, this bit is automatically
set to “0”.
Each interrupt request bit can be set to “0”, but cannot be set to
“1”, by software.
Interrupt Enable Bits
The interrupt enable bits control the acceptance of the corre-
sponding interrupt requests. When an interrupt enable bit is set to
“0”, the acceptance of the corresponding interrupt request is dis-
abled. If an interrupt request occurs in this condition, the
corresponding interrupt request bit is set to “1”, but the interrupt
request is not accepted. When an interrupt enable bit is set to “1”,
the acceptance of the corresponding interrupt request is enabled.
Each interrupt enable bit can be set to “0” or “1” by software.
The interrupt enable bit for an unused interrupt should be set to
“0”.
Interrupt Enable Setting
The following interrupt sources can be set to valid or invalid by the
interrupt source set register (000A16).
Key-on wakeup
UART1 bus collision detection interrupt
A/D conversion
Timer 1 interrupt
Interrupt edge selection
The valid edge of external interrupt INT0 and INT1 can be selected
by the interrupt edge selection bit of the interrupt edge selection
register (003A16), respectively.
Set bit 2 of interrupt edge selection register to “1”.
Key-on wakeup
Enable/disable of a key-on wakeup of pins P00, P04, and P06 can
be selected by the key-on wakeup enable bit of the interrupt edge
selection register (003A16), respectively.
Note: For key-on wakeup, UART1 bus collision detection, A/D conversion and Timer 1 interrupt,
even if interrupt valid bit (000A16) is set “0: Invalid”,
interrupt discrimination bit (000B16) is set to “1: interrupt occurs”
when corresponding interrupt request occurs.
But corresponding interrupt request bit (003C16, 003D16) is not set to “1”.
Interrupt disable flag I
Interrupt acceptance
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
Timer 1 interrupt request
Timer 1 interrupt valid bit
A/D conversion interrupt request
A/D conversion interrupt valid bit
A/D conversion interrupt
discrimination bit
Timer 1 interrupt
discrimination bit
A/D conversion/
Timer 1 interrupt
request bit
UART1 bus collision detection
interrupt request
UART1 bus collision detection
interrupt valid bit
Key-on wakeup interrupt request
Key-on wakeup interrupt valid bit
Key-on wakeup interrupt
discrimination bit
UART1 bus
collision detection
interrupt
discrimination bit
Key-on wakeup/
UART1 bus collision
detection interrupt
request bit