參數(shù)資料
型號(hào)： M37545GF-XXXGP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP32
封裝： 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件頁數(shù)： 11/65頁
文件大?。?/td> 782K
代理商： M37545GF-XXXGP
Rev.1.07
Mar 19, 2009
Page 17 of 60
REJ03B0140-0107
7545 Group
I/O PORTS
[Direction registers] PiD
The I/O ports have direction registers which determine the input/
output direction of each pin. Each bit in a direction register
corresponds to one pin, and each pin can be set to be input or
output.
When “1” is set to the bit corresponding to a pin, this pin
becomes an output port. When “0” is set to the bit, the pin
becomes an input port.
When data is read from a pin set to output, not the value of the
pin itself but the value of port latch is read. Pins set to input are
floating, and permit reading pin values.
If a pin set to input is written to, only the port latch is written to
and the pin remains floating.
[Pull-up control register] Pull
By setting the pull-up control register (address 001616), port P0
can exert pull-up control by program. However, pins set to
output are disconnected from this control and cannot exert pull-
up control.
[Port output mode selection register] PMOD
By setting the port output mode selection register (address
001716), CMOS output or N-channel open-drain can be selected
for ports P1, P2, P3 by program.
Fig. 13 Structure of pull-up control register
Fig. 14 Structure of port output mode selection register
Port P04
Port P01
Port P00
0: Pull-up transistor off
1: Pull-up transistor on
b7
b0
Port P02
Port P03
Port P05
Port P06
Port P07
Pull-up control register
(PULL: address 001616, initial value: 0016)
Table 7
I/O port function table
Pin
Name
Input/Output
I/O format
Non-port function
Related SFRs
Diagram No.
P00
P07
Port P0
I/O individual
bits
CMOS compatible input
level
CMOS 3-state output
Key input interrupt
Pull-up control register
Key-on wakeup pin selection register
Key-on wakeup edge selection regis-
ter
(1)
P10
P11
Port P1
CMOS compatible input
level
CMOS 3-state output or
N-channel open drain
RLSS-only pin
Port output mode selection register
(2)
P20/INT0
P21/INT1
Port P2
External interrupt input
Interrupt edge selection register
Port output mode selection register
(3)
P22
P27
Port output mode selection register
(2)
P30
P37
Port P3
Port output mode selection register
(2)
P40, P41
Port P4
CMOS compatible input
level
CMOS 3-state output
RLSS-only pin
(4)
P42/CARR
Carrier wave output for
remote-control transmitter
Carrier wave control register
(5)
Port P34P37
Port P20P23
Port P10P11
0: CMOS output
1: N-channel open-drain
b7
b0
Port P24P27
Port P30P33
Disable (returns “0” when read)
Port output mode selection register
(PMOD: address 001716, initial value: 0016)
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參數(shù)描述
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